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3.5.5 EDO RAS# Precharge Time
DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely
as the result of a single request. This option allows you to determine the number of CPU clocks
allocated for the Row Address Strobe to accumulate its charge before the DRAM is refreshed. If
insufficient time is allowed, refresh may be incomplete and data lost.
Options
3 / 4 (*)
3.5.6 EDO DRAM Read/Write BURST
This sets the timing for burst mode reads/write from EDO DRAM. Burst read and write requests
are generated by the CPU in four separate parts. The first part provides the location within the
DRAM where the read or write is to take place while the remaining three parts provide the actual
data. The lower the timing numbers, the faster the system will address memory.
Options
Description
x222
Read/Write DRAM timings are 2-2-2
x333
Read/Write DRAM timings are 3-3-3
3.5.7 DRAM Data Integrity Mode
When enabled, the BIOS will use ECC (Error Checking and Correcting) protocol to increase
integrity of system data. When ECC is selected, all memory modules the system used must support
ECC.
Options
ECC / Non-ECC (*)
3.5.8 CPU-TO-PCI Posting
This item allows you to select the cycles are treated as normal I/O write transaction or not.
Options
Enabled (*) / Disabled
3.5.9 System BIOS Cacheable
When enabled, accesses to the system BIOS will be cached.
Options
Enabled (*) / Disabled
3.5.10 Video BIOS Cacheable
When enabled, access to the video BIOS will be cached.
Options
Enabled / Disabled (*)
3.5.11 Video RAM Cacheable
When enabled, access to the video memory located at A0000H to BFFFFH will be cached.
Options
Enabled / Disabled (*)
