IWILL kv200, Руководство пользователя

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Chapter 4 BIOS Setup
DRAM Settings
The first chipset settings deal with CPU access to dynamic
random access memory (DRAM). The default timings have
been carefully chosen and should only be altered if data is
being lost. Such a scenario might well occur if your system
had mixed speed DRAM chips installed. Longer delays
might result, however this preserves the integrity of the data
held in the slower memory chips.
4.6.1 SDRAM Cycle Length
When synchronous DRAM is installed, the number of clock
cycles of CAS latency depends on the DRAM timing. Do not
reset this field from the default value specified by the system
designer.
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4.6.2 Bank Interleave
Select numbers of Bank to Bank to realize fast and
seamless data access mode amony many different pages.
( D P S y B e l u a V t l u a f e D s k n a B 4 , s k n a B 2 , )
4.6.3 DRAM Clock
This field allows you to select the DRAM operating frequency
to get better performance.
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