Rev 1.1
Page 15 of 61
i.MX6 Pico ITX - SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.3
Boot Mode Setting
i.MX6 CPU boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM
core to begin execution starting from the on-chip boot ROM. The i.MX6 Boot ROM code uses the state
of the internal register BOOT_MODE [1:0] as well as the state of various eFUSEs and/or GPIO settings to
determine the boot flow behaviour of the device.
i.MX6 Pico ITX SBC supports Boot Mode Switch (SW4) which is physically located in the top of the PCB.
This Switch is used to select the boot mode setting of i.MX6 CPU as explained in the below table. SPI
Flash used as Default Booting Media.
Table 2: Boot Mode Settings Truth Table
Boot Mode Setting
On i.MX6 Pico ITX -SBC
Description
Switch (SW4) Position
POS 1
POS 2
Image
Internal Boot Mode
(Default)
In this mode, i.MX6 boot
media is selected by GPIO
Pin’s settings
OFF
ON
Boot From eFuses
In this mode, i.MX6 boot
media is selected by i.MX6
eFUSE settings
Note: i.MX6 eFuse setting is
NOT modified by iWave from
silicon shipped value
.
OFF
OFF
Serial Downloader
Mode
In this mode, i.MX6 boot
device can be Programmed
through
its
USB
OTG
interface using MFG Tool
ON
OFF
ON – High
OFF - Low
