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3480-ddc.ib.rev8.doc 

page 19 of 20

 17/10/2007 

 

Glossary of terms 

 
8B/10B 

Eight to Ten Bit Conversion. 

ASI 

Asynchronous Serial Interface. 

ASI-C 

ASI Coaxial cable. 

ASI-O 

ASI Fibre optic cable. 

B3ZS 

Bipolar with Three Zero Substitution. 

BB Baseband. 
BER 

Bit Error Rate. 

CCIR 

Comite Consultatif International des Radiocommunications. 

CCITT 

Comite Consultatif International Telephonique et Telegraphique. 

CPLD 

Custom Programmable Logic Device. 

DJ Deterministic 

Jitter. 

DTVC 

Digital Television by Cable. 

DVB 

Digital Video Broadcasting. 

DVG 

Digital Video Generator. 

EBU 

European Broadcasting Union. 

EBU 

European Broadcasting Union. 

ETS 

European Telecommunication Standard. 

ETSI 

European Telecommunications Standards Institute. 

FEC 

Forward Error Correction. 

FIFO 

First In First Out. 

FPGA 

Field Programmable Gate Array. 

G.703 

ITU CCITT recommendation G.703. 

HDB3 

High Density Bi-polar of order 3. 

IF Intermediate 

Frequency. 

IRD 

Integrated Receiver Decoder. 

ITU 

International Telecommunications Union. 

LSB 

Least Significant Bit. 

LVDS 

Low Voltage Differential Signalling. 

Mb/s 

Megabits per second. 

MPEG  

Moving Pictures Experts Group. 

MPEG 

Motion Picture Experts Group. 

MSB  

Most Significant Bit. 

MSB 

Most Significant Bit. 

MUX  

Multiplex. 

NO 

Normally open contact set. 

NC 

Normally closed contact set. 

NRZ 

Non Return to Zero. 

PDH 

Plesiochronic Digital Hierarchy. 

PRBS 

Pseudo Random Binary Sequence. 

QAM 

Quadrature Amplitude Modulation. 

QEF 

Quasi Error Free. 

QPSK Quarternary 

Phase Shift Keying. 

R & S 

Rohde & Schwarz. 

RF Radio 

Frequency. 

RJ Random 

Jitter. 

RS Reed 

Solomon. 

SDI 

Serial Digital Interface. 

SMATV 

Satellite Master Antenna Television. 

SPI 

Synchronous Parallel Interface MPEG2. 

SSI 

Synchronous Serial Interface. 

TDM 

Time Division Multiplex. 

TS Transport 

Stream. 

TV Television. 
 
 

IRT 

Communications 

www.irtcommunications.com

Содержание DDC-3480

Страница 1: ...e Internet at http www irtelectronics com I R T Electronics Pty Ltd A B N 35 000 832 575 26 Hotham Parade ARTARMON N S W 2064 AUSTRALIA National Phone 02 9439 3744 Fax 02 9439 7439 International 61 2...

Страница 2: ...Connections 9 Front rear panel connector diagrams 9 Operation 10 Basic operation 10 Front indicators 10 Maintenance storage 11 Warranty service 11 Equipment return 11 Characteristics of signal types 1...

Страница 3: ...lower processing speed requirements The ASI O interface is of limited usefulness due to the specification of multimode fibre with only a short haul capability Optical transport of ASI can be better ac...

Страница 4: ...MPEG2 TS formats Interleaving or de interleaving Reed Solomon insertion correction Spectrum dispersion correction Signal monitoring for remote alarm indications DDC 3470 only Block diagram DDC 3480 8B...

Страница 5: ...ink 2 pin 0 1 IDC male connector Power Requirements 28 Vac CT 14 0 14 or 16 Vdc Power consumption 5 VA Other Temperature range 0 50 C ambient Mechanical Mounts in IRT FRU 1030 1 RU 19 rack chassis wit...

Страница 6: ...t The G 703 output is the processed TS format The G 703 output is disabled during loss of ASI input Input Loss Alarms The Input Loss Alarm will be asserted in the absence of a valid ASI input Input TS...

Страница 7: ...ry to convert from one rate to another involve changing firmware crystals and other components in addition to setting links detailed below After making these changes the whole module must be tested fo...

Страница 8: ...etween signal earth and chassis earth No attempt should be made to break this connection Installation in frame or chassis The 3400 series of modules may only be mounted in IRT s FRU 1030 type 1 RU cha...

Страница 9: ...t is available This is set by link LK 5 and should be set to correspond to the length of cable connected to the output This is necessary only if a shaped characteristic is required for short cable len...

Страница 10: ...cted at the input for a given time MPEG 2 TS always contain a sync byte every 204 or 188 bytes irrespective of data content Therefore if 2040 or more consecutive 1 s or 0 s are been detected then the...

Страница 11: ...inable from the component supplier Equipment return Before arranging service ensure that the fault is in the unit to be serviced and not in associated equipment If possible confirm this by substitutio...

Страница 12: ...ta transfer is synchronised to the Byte clock of the MPEG transport stream The data to be transmitted are MPEG 2 transport packets The data signals are synchronised to the clock depending on the trans...

Страница 13: ...rial data stream The disparity characteristics of the code maintain DC balance Special characters are defined as extra code points beyond the need to encode a Byte of data One in particular is used to...

Страница 14: ...e PRBS registers is initiated at the start of every eight transport packets To provide an initialisation signal for the de scrambler the MPEG 2 sync Byte of the first transport packet in a group of ei...

Страница 15: ...Byte stream by the input switch Each branch is a First In First Out FIFO shift register with depth Mj cells where M 17 N I N 204 error protected frame length I 12 interleaving depth branch index The c...

Страница 16: ...dB Electrical characteristics CCITT G 703 34368 Kb s Cable type Coaxial Impedance 75 Signal level 1 0 V Nominal pulse width 14 55 ns Code conversion HDB3 Pulse shape Fig 17 G 703 Jitter at input port...

Страница 17: ...simplifying system design Note that the ASI signal is polarity sensitive Although most 270 Mb s SDI DA s and switchers will pass ASI signals the line drivers used usually have both inverted and non i...

Страница 18: ...11 12 GHz satellite services ETS 300 429 Digital broadcasting systems for Television sound and data services framing structure channel coding and modulation for cable systems ETS 300 473 Digital broad...

Страница 19: ...U CCITT recommendation G 703 HDB3 High Density Bi polar of order 3 IF Intermediate Frequency IRD Integrated Receiver Decoder ITU International Telecommunications Union LSB Least Significant Bit LVDS L...

Страница 20: ...17 10 2007 Drawing index Drawing Sheet Description 804154 1 DDC 3480 45 ASI to G 703 circuit schematic 804154 2 DDC 3480 8 ASI to G 703 circuit schematic I R T C o m m u n i c a t i o n s w w w i r t...

Страница 21: ...5 58 60 64 85 18 41 28 38 101 79 44 45 46 47 87 89 97 94 169 167 83 39 30 25 17 EPF10K10QC208 DDC 3480 TO G703 CONVERTER 34 or 45 9 1 2 3 4 5 6 10 1 3 4 2 8 7 5 EPC1441 DCLK ConfDone nConf nStatus DAT...

Страница 22: ...0 TO G703 CONVERTER 9 1 2 3 4 5 6 10 1 3 4 2 8 7 5 EPC1441 DCLK ConfDone nConf nStatus DATA0 mSel0 mSel1 nCE 2 B1 155 105 52 156 U9 PART J7 U11 B1 108 107 154 RNEG RCLK 15 17 16 8 U17A 1 2 3 U17A 5 4...

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