3480-ddc.ib.rev8.doc
page 12 of 20
17/10/2007
Characteristics of signal types
Coding characteristics
G.703:
The
HDB3
(High Density Bi-polar of order 3) code as defined in G.703 for 34,368 Kbits/s is as follows:
Binary 1 bits are represented by alternate positive and negative pulses and binary 0 bits by spaces.
Exceptions are made when strings of successive 0 bits occur in the binary signal.
Each block of 4 successive zeros is replaced by 000V or B00V where B is an inserted pulse of the correct
polarity and V is an inserted pulse violating the polarity rule. The choice of 000V or B00V is made so that
the number of B pulses between consecutive V pulses is odd so that successive V pulses are of alternate
polarity and so no DC component is introduced.
The
B3ZS
(Bipolar with Three Zero Substitution) (Also designated
HDB2
- High Density Bi-polar of order 2) code
as defined in G.703 for 44,736 Kbits/s is as follows:
Binary 1 bits are represented by alternate positive and negative pulses and binary 0 bits by spaces.
Exceptions are made when strings of successive 0 bits occur in the binary signal.
Each block of 3 successive zeros is replaced by 00V or B0V. The choice of 00V or B0V is made so that the
number of B pulses between consecutive V pulses is odd, so that successive V pulses are of alternate polarity
and so no DC component is introduced.
Synchronous Parallel Interface (SPI)
SPI is a system for parallel transmission of variable data rates. The data transfer is synchronised to the Byte clock of
the MPEG transport stream.
The data to be transmitted are MPEG-2 transport packets. The data signals are synchronised to the clock depending
on the transmission rate.
The parallel interface has three allowable transmission formats:
188 byte packets
204 Byte packets (188 data Bytes + 16 dummy Bytes)
204 byte packets (188 data Bytes + 16 additional valid Bytes)
The clock, data and synchronisation signals are transmitted in parallel. They comprise 8 data bits together with one
(MPEG-2) PSYNC signal and a DVALID signal.
The DVALID signal indicates in the 204 Byte mode that the additional space is filled with dummy Bytes.
All signals are synchronous to the clock signal. The signals are coded in NRZ form.
The clock is a square wave signal where the 0-1 transition represents the data transfer time. The clock frequency
depends on the transmission rate. The frequency corresponds to the useful bitrate of the MPEG2 transport layer and
shall not exceed 13.5 MHz.
Clock
1
pair
Data (0-7)
8 pair
TX
DVALID
1
pair
RX
PSYNC
1
pair
= 11 pair in total.
Electrical characteristics of the interface
Each of the eleven line drivers (source) has a balanced output and each line receiver (destination) a balanced input
employing LVDS drivers / receivers. All digital signal time intervals are measured between the half-amplitude
points.
Logic convention
A binary 1 is represented by the non-inverted output being positive with respect to the inverted output.
A binary 0 is represented by the non-inverted output being negative with respect to the inverted output.
IRT
Communications
www.irtcommunications.com
