Inventec P47 series, Руководство по обслуживанию

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K800G4 BMC Specification
22
1 2 3 4 5 6 7
Sensor Number 0x60 0x61 0xB0 0xB1 0xB2 0xB3 0xB4
Sensor Name PSU_STATUS_01 PSU_STATUS_02 MEM_STATUS_01 MEM_STATUS_02 MEM_STATUS_03 MEM_STATUS_04 MEM_STATUS_05
Sensor Type 0x08 0x08 0x0C 0x0C 0x0C 0x0C 0x0C
Event Type 0x6F 0x6F 0x6F 0x6F 0x6F 0x6F 0x6F
Entity ID 0x0A 0x0A 0x20 0x20 0x20 0x20 0x20
Instance 0x00 0x01 0x00 0x00 0x00 0x00 0x00
Initialization 0x67 0x67 0x67 0x67 0x67 0x67 0x67
Capabilities 0x40 0x40 0x60 0x60 0x60 0x60 0x60
AE/LTR Mask 0x004B 0x004B 0x7FFF 0x7FFF 0x7FFF 0x7FFF 0x7FFF
AE/LTR (BIT) 0/1/3/6/ 0/1/3/6/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
DE/UTR Mask 0x004A 0x004A 0x7FFF 0x7FFF 0x0000 0x0000 0x0000
DE/UTR (BIT) 1/3/6/ 1/3/6/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
DR/ST/RT Mask 0x004B 0x004B 0x7FFF 0x7FFF 0x7FFF 0x7FFF 0x7FFF
DR/ST/RT (BIT) 0/1/3/6/ 0/1/3/6/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
SRS/SD 0x0000 0x0000 0x8101 0x8101 0x8101 0x8101 0x8101
SRS/SD (BIT) 0/8/15/ 0/8/15/ 0/8/15/ 0/8/15/ 0/8/15/
Table B2 , Compact Sensor Record
8 9 10 11 12 13 14
Sensor Number 0xB5 0xB6 0xB7 0xFE 0xFA 0xFD 0xF2
Sensor Name MEM_STATUS_06 MEM_STATUS_07 MEM_STATUS_08 SEL WATCHDOG2 PWR_UNIT_STATUS PSU_REDUNANCY
Sensor Type 0x0C 0x0C 0x0C 0x10 0x23 0x09 0x08
Event Type 0x6F 0x6F 0x6F 0x6F 0x6F 0x6F 0x0B
Entity ID 0x20 0x20 0x20 0x06 0x00 0x0A 0x0A
Instance 0x00 0x00 0x00 0x02 0x09 0x00 0x09
Initialization 0x67 0x67 0x67 0xE7 0x7F 0x67 0x7F
Capabilities 0x60 0x60 0x60 0x40 0x68 0x40 0x68
AE/LTR Mask 0x7FFF 0x7FFF 0x7FFF 0x0034 0x010F 0x0000 0x0003
AE/LTR (BIT)
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
2/4/5/ 0/1/2/3/8/ 0/1/
DE/UTR Mask 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
DE/UTR (BIT)
DR/ST/RT Mask 0x7FFF 0x7FFF 0x7FFF 0x0034 0x010F 0x0064 0x0003
DR/ST/RT (BIT)
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
0/1/2/3/4/5/6/7/8/9/10/
11/12/13/14/
2/4/5/ 0/1/2/3/8/ 2/5/6/ 0/1/
SRS/SD 0x8101 0x8101 0x8101 0x0000 0x8101 0x8101 0x8101
SRS/SD (BIT) 0/8/15/ 0/8/15/ 0/8/15/ 0/8/15/ 0/8/15/ 0/8/15/

AM/LTR : Assertion Event Mask / Lower Threshold Reading Mask

DEM/UTR : De-assertion Event Mask / Upper Threshold Reading Mask

DE/UTR: Discrete Reading Mask / Settable Threshold Mask, Readable Threshold Mask

LNR : Lower non-recoverable Threshold

LC : Lower critical Threshold

LNC : Lower non-critical Threshold

UNC : Upper non-critical Threshold

UC : Upper critical Threshold

UNR : Upper non-recoverable Threshold