Open-X™ 8M Development Kit based on the NXP i.MX8™ Processor User Guide Version 1.0
37
Copyright Intrinsyc Technologies Corporation
Pin#
CAM1 (J1500)
CAM2 (J1600)
Description
9
NVCC_1V8
NVCC_1V8
Power output. Connected to
PMIC SW4 switch output.
Default is +1.8V. Maximum
current 300mA
10
NVCC_1V8
NVCC_1V8
Power output. Connected to
PMIC SW4 switch output.
Default is +1.8V. Maximum
current 300mA
13
CSI_nRST_1V8
CSI_nRST_1V8
Output. Connected to i.MX 8M8
gpio1.IO[6]. Default use is for
camera reset.
14
CAM1_nPWDN_1
V8
CAM1_nPWDN_1V8
Output. Connected to i.MX 8M8
gpio1.IO[3]. Default use is for
camera standby.
15
CSI_I2C_SCL
CSI_I2C_SCL
Output. Connected to i.MX 8M8
I2C3 bus. Default use is for
camera CSI I2C clock interface.
16
CSI_I2C_SDA
CSI_I2C_SDA
Input / output. Connected to i.MX
8M8 I2C3 bus. Default use is for
camera CSI I2C data interface.
17
CAM1_MCLK0
CAM2_MCLK0
Output. Connected to i.MX 8M8
gpio1.IO[15]. Default use is for
camera master clock. Maximum
24MHz.
20
MIPI_CSI0_LANE0
_N
MIPI_CSI1_LANE0_N
Input. MIPI CSI0 / CSI1 / CSI2
data lane 0
21
MIPI_CSI0_LANE0
_P
MIPI_CSI1_LANE0_P
Input. MIPI CSI0 / CSI1 / CSI2
data lane 0
23
MIPI_CSI0_CLK_
N
MIPI_CSI1_CLK_N
Input. MIPI CSI0 / CSI1 / CSI2
clock lane
24
MIPI_CSI0_CLK_P
MIPI_CSI1_CLK_P
Input. MIPI CSI0 / CSI1 / CSI2
clock lane
26
MIPI_CSI0_LANE1
_N
MIPI_CSI1_LANE1_N
Input. MIPI CSI0 / CSI1 / CSI2
data lane 1
27
MIPI_CSI0_LANE1
_P
MIPI_CSI1_LANE1_P
Input. MIPI CSI0 / CSI1 / CSI2
data lane 1
29
MIPI_CSI0_LANE2
_N
MIPI_CSI1_LANE2_N
Input. MIPI CSI0 / CSI1 / CSI2
data lane 2
30
MIPI_CSI0_LANE2
_P
MIPI_CSI1_LANE2_P
Input. MIPI CSI0 / CSI1 / CSI2
data lane 2
32
MIPI_CSI0_LANE3
_P
MIPI_CSI1_LANE3_P
Input. MIPI CSI0 / CSI1 / CSI2
data lane 3
33
MIPI_CSI0_LANE3
_N
MIPI_CSI1_LANE3_N
Input. MIPI CSI0 / CSI1 / CSI2
data lane 3
12,18,35,3
6,37,38,39
,40,41
NU
NU
Not Used
Note:
A connection from the camera connectors on the carrier board to the camera adapter board is
established by a 41-pin cable assembly from JAE Electronics (part number JF08R0R041020MA)