Intrinsyc Open-
Q™ 605 SBC User Guide and HW Specification
V. 1.4
28
Copyright Intrinsyc Technologies Corporation
The table below outlines the pin information (primary and alternate functions) of the J3600 expansion connector:
Table 3-13 – Summary of GPIOs
PIN
#
Signal
Default Function
Description
Alternate
Functions
Description
11
GP92_FOCUS_N
QCS605:
QUP_L3(4)
(GPIO_92)
QUP 4, lane 3:
UART_RX
13
GP91_SNAPSHOT_N QCS605:
QUP_L2(4)
(GPIO_91)
QUP 4, lane 2:
UART_TX
QDSS_CTI_TRIG1_IN_B
QDSS trigger input B
21
GP0_QUP0_L0
QCS605:
QUP_L0(0)
(GPIO_0)
Configurable I/O :
QUP 0, lane 0:
UART_CTS
QUP_L0(0)
Configurable I/O :
QUP 0, lane 0: SPI_MISO
QUP 0, lane 0: I2C_SDA
30
GP1_QUP0_L1
QCS605:
QUP_L1(0)
(GPIO_1)
Configurable I/O :
QUP 0, lane 1:
UART_RFR
QUP_L1(0)
Configurable I/O :
QUP 0, lane 1: SPI_MOSI
QUP 0, lane 1: I2C_SCL
19
GP2_QUP0_L2
QCS605:
QUP_L2(0)
(GPIO_2)
Configurable I/O :
QUP 0, lane 2:
UART_TX
QUP_L0(0)
Configurable I/O :
QUP 0, lane 2: SPI_SCLK
28
GP3_QUP0_L3
QCS605:
QUP_L3(0)
(GPIO_3)
Configurable I/O :
QUP 0, lane 3:
UART_RX
QUP_L3(0)
Configurable I/O :
QUP 0, lane 3: SPI_CS0
34
GP41_QUP3_L0
QCS605:
QUP_L0(3)
(GPIO_41)
Configurable I/O :
QUP 3, lane 0:
UART_CTS
QUP_L0(3)
QDSS_TRACEDATA_6A
Configurable I/O :
QUP 3, lane 0: SPI_MISO
QUP 3, lane 0: I2C_SDA
QDSS trace data bit 6 A
29
GP42_QUP3_L1
QCS605:
QUP_L1(3)
(GPIO_42)
Configurable I/O :
QUP 3, lane 1:
UART_RFR
QUP_L1(3)
QDSS_TRACEDATA_7A
Configurable I/O :
QUP 3, lane 1: SPI_MOSI
QUP 3, lane 1: I2C_SCL
QDSS trace data bit 7 A
27
GP43_QUP3_L2
QCS605:
QUP_L2(3)
(GPIO_43)
Configurable I/O :
QUP 3, lane 2:
UART_TX
QUP_L2(3)
Configurable I/O :
QUP 3, lane 2: SPI_SCLK