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Application Note 1662

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AN
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2

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be

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, 2

011

FIGURE 2. BOTTOM LAYER

PCB Layout 

 (Continued)

Содержание ISL97682IRTZEVALZ

Страница 1: ...e provided for easily adjust the LED maximum DC current Please refer to the ISL97682IRTZEVALZ Evaluation Board Schematic on page 2 for more details LED dimming frequency and duty cycle As mentioned in step 4 above when the shunt on JP20 is connected to the upper position FPWM DPWM pin is connected to VDC the device enters direct PWM mode which means both the LED dimming frequency and the duty cycl...

Страница 2: ...R9 10k C15 8 2nF C3 33pF TP1 LX TP2 VOUT TP3 CH1 TP5 CH3 VDC P5 AGND P6 AGND P7 AGND P8 AGND P9 PGND P10 PGND 2 layer board Connect top layer PGND and bottom layer AGND F1 2A Fuse JP14 R11 100k R10 0 R13 Open R12 27k JP15 JP17 EN can be connected in the following ways to enable disable the device 1 Connected it to VIN directly on JP1 to enable 2 Connected it to GND directly on JP1 to disable 3 Dir...

Страница 3: ...Application Note 1662 3 AN1662 0 October 11 2011 PCB Layout FIGURE 1 TOP SILKSCREEN LAYER TOP LAYER ...

Страница 4: ...Application Note 1662 4 AN1662 0 October 11 2011 FIGURE 2 BOTTOM LAYER PCB Layout Continued ...

Страница 5: ...capacitors C2 0 1µF 50V 603 C3 33pF 603 C4 1µF 16V 603 C5 4 7µF 50V 1210 Murata GRM32ER71H475KA88L C6 4 7µF 50V 1210 C7 Place Holder 1210 Not Populated C8 Place Holder 1210 C9 100pF 50V 603 General purpose Ceramic X5R X7R capacitors C10 3 3nF 50V 603 C11 1nF 50V 603 C12 Place Holder 603 C13 1nF 50V 603 C14 Place Holder 603 C15 8 2nF 603 F1 2A Fuse 1206 Bel Fuse Inc C1Q 2 U1 QFN16 3MM Intersil ISL9...

Страница 6: ... TEST POINT Keystone Electronics 5010 TP2 VOUT TEST POINT TP3 CH1 TEST POINT TP4 CH2 TEST POINT TP5 CH3 TEST POINT TP6 CH4 TEST POINT TP7 VDC TEST POINT TP8 RSET TEST POINT TP9 FSW PHS TEST POINT P5 AGND TEST POINT Keystone Electronics 5011 P6 AGND TEST POINT P9 PGND TEST POINT P1 PVIN POWERPOST Mill Max 3156 1 00 00 00 00 08 0 P2 VIN POWERPOST P3 EN POWERPOST P4 PWMI POWERPOST P7 AGND POWERPOST P...

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