2
AN1185.0
April 19, 2005
ISL59442EVAL1 Top View
TABLE 1. LOGIC TABLE
S0
S1
HIZ
OUT
0
0
0
IN0
1
0
0
IN1
0
1
0
IN2
1
1
0
IN3
-
-
1
High Z
* C
b1
, C
b2
are approximate PCB trace capacitances.
FIGURE 2A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
* C
b1
is approximate PCB trace capacitance.
FIGURE 2B. TEST CIRCUIT FOR 50
Ω
OR 75
Ω
TERMINATIONS
* C
b1
is approximate PCB trace capacitance.
FIGURE 2C. BACK-TERMINATED TEST CIRCUIT FOR CABLE APPLICATION
ISL59442
50
Ω
V
IN
500
Ω
R
L
OR
75
Ω
*C
b2
~3pF
R
S
, 0
Ω
~0.5pF
C
b1
ISL59442
R
S
V
IN
475
Ω
TEST
~0.5pF
50
Ω
OR
75
Ω
50
Ω
OR
75
Ω
50
Ω
OR
75
Ω
R
L
EQUIPMENT
C
b1
ISL59442
R
S
C
b1
V
IN
50
Ω
OR 75
Ω
TEST
~0.5pF
50
Ω
OR
75
Ω
50
Ω
OR
75
Ω
EQUIPMENT
Application Note 1185
