4
AN1270.0
September 27, 2006
ISL55142IVZ Evaluation Board Schematic
FIGURE 8. ISL55141IVZ TSSOP SINGLE COMPARATOR EVALUATION BOARD SCHEMATIC
S1 - POWER-DOWN CONTROL
SPDT - CENTER OFF
C7
+4.7µF
R1
50
Ω
R2
50
Ω
J9-CVB - Banana Jack
C5
0.1µF
VDD
CVB_BUS
GND
GND
DIF--
DIF+
TP01-QA_VOL
DIF--
DIF+
TP02-QB_VOL
DIF--
DIF+
TP06_CVB
QA_J3
QB_J4
PD - BN_J5
C8
+4.7µF
J10-GND - Banana Jack
J11-CVA - Banana Jack
C6
0.1µF
CVA_BUS
GND
DIF--
DIF+
TP05_CVA
VOL - Banana Jack
C1
+4.7µF
C2
0.1µF
DIF--
DIF+
TP03-VOH_VOL
VOH - Banana Jack
QB0
QA0
1
2
JP01
VOL = VEE
1
2
JP02
VOL = GND
1
2
JP03
VEE = GND
VOL
VEE
GND
VCC
VOH
VOL
GND - Banana Jack
VEE - Banana Jack
C4
+4.7µF
C3
0.1µF
VCC
DI
F--
DI
F+
TP04_VCC_VEE
GND
GND
GND
CVB_BUS
CVA_BUS
CVB_BUS
CVA_BUS
VEE
VINP
VOL
VOL
VEE
PD
VOL
VEE
R14
0
Ω
R18
0
Ω
R20
NOT POPULATED
DIF--
DIF+
TP07-VINP
VINP_J8
GND
VINP
VCC - Banana Jack
PD
14
CVB
12
VINP
11
CVA
10
VCC
9
VEE
8
VEE
1
QA
4
QB
5
VOL
6
VOH
7
ISL55141_TSSOP
Application Note 1270
