Intersil HI5905EVAL2, Руководство пользователя

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3-3
The analog and digital supplies are also kept separate on
the evaluation board and should be driven by clean linear
regulated supplies. The external power supplies are hooked
up with the twisted pair wires soldered to the plated through
holes 5VAIN, +5VAIN1, -5VAIN, +5VDIN,
+5VD1IN, +5VD2IN, -5VDIN, AGND and DGND near the
analog prototyping area. +5VDIN, +5VD1IN, +5VD2IN
and -5VDIN are digital supplies and are returned to DGND.
+5VAIN, +5VAIN1 and -5VAIN are the analog supplies and
are returned to AGND. Table 1 lists the operational supply
voltages, typical current consumption and the evaluation
board circuit function being powered. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade. Sample Clock Driver, Timing and I/O
In order to ensure rated performance of the HI5905, the duty
cycle of the sample clock should be held at 50%
±
5%. It
must also have low phase noise and operate at standard
TTL levels.
A voltage comparator (U3) with TTL output levels is provided
on the evaluation board to generate the sampling clock for
the HI5905 when a sinewave (<
±
3V) or squarewave clock is
applied to the CLK input (J2) of the evaluation board. A
potentiometer (VR1) is provided to allow the user to adjust
the duty cycle of the sampling clock to obtain the best
performance from the ADC and to allow the user to
investigate the effects of expected duty cycle variations on
the performance of the converter. The HI5905 clock input
trigger level is approximately 1.5V. Therefore, the duty cycle
of the sampling clock should be measured at this 1.5V
trigger level. Test point TP2 provides a convenient point to
monitor the sample clock duty cycle and make any required
adjustments.
Figure 3 shows the sample clock and digital data timing
relationship for the evaluation board. The data
corresponding to a particular sample will be available at the
digital data outputs of the HI5905 after the data latency time,
t
LAT
, of 4 sample clock cycles plus the HI5905 digital data
output delay, t
OD
. Table 2 lists the values that can be
expected for the indicated timing delays. Refer to the HI5905
data sheet for additional timing information.
TABLE 1. HI5905EVAL2 EVALUATION BOARD POWER
SUPPLIES
POWER
SUPPLY
NOMINAL
VALUE
CURRENT
(TYP)
FUNCTION(S)
SUPPLIED
+5VAIN 5.0V
±
5% 80mA Op Amps, A/D AV
CC
-5VAIN -5.0V
±
5% 30mA Op Amps
+5VDIN 5.0V
±
5%3 60mA CLK Comparator,
Inverter
D0-D13 D-FF’s
+5VD1IN 5.0V
±
5% 14mA A/D DV
CC1
+5VD2IN 5.0V
±
5% 6mA A/D DV
CC2
-5VDIN -5.0V
±
5% 3mA CLK
Comparator
SINEWAVE CLK IN
HI5905 SAMPLE
CLOCK INPUT
HI5905 DIGITAL
DATA OUTPUT
CLOCK OUT
DIGITAL DATA OUTPUTS
t
PD2
(74ALS574)
t
PD1
DATA N
DATA N DATA N-1
t
OD
(J2)
(CLK AT TP2)
(D0 - D13)
(CLK AT TP1, P2-C20 OR P2-31)
DATA N-1
FIGURE 3. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS
Application Note 9785