IRDC3073EVAL
3
Rev. 1.0
06/30/03
www.irf.com
The four layers for IRU3073 evaluation board are shown
in Figures 2.1-2.4. The layout is designed both for direct
FET package and SOIC package for power MOSFETs.
The input capacitors are all located close to the
MOSFETs. All the decoupling capacitors and feedback
components are located close to IC. The feedback re-
sistors are tied to the output voltage at the point of regu-
lation.
The middle layers are dedicated to Power Ground and
Analog Ground. Analog Ground is kept separated from
the Power Ground and it is connected at a single point
as shown in figure 2.3.
LAYOUT
Figure 2.1 - Top layer of evaluation-board for IRU3073.