Inter-m GEQ-1231D, Руководство по обслуживанию

Страница: 8 / 32

13 12
PACKAGE & LEAD FRAME MATERIAl
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
PACKAGZ
Note : Dimension “*” does not include moid flash.
ADSP-21065L DSP MICROCOMPUTER
SUMMARY
– High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and
Industrial Applications
– Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle
– 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-Point Arithmetic
– 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral
– I
2 S Support, for Eight Simultaneous Receive and Transmit Channels
KEY FEATURES
– 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance
– User-Configurable 544 Kbits On-Chip SRAM Memory
– Two External Port, DMA Channels and Eight Serial Port, DMA Channels
– SDRAM Controller for Glueless Interface to Low Cost External Memory (@66 MHz)
– 64M Words External Address Range
– 12 Programmable I/O Pins and Two Timers with Event Capture Options
– Code-Compatible with ADSP-2106x Family
– 208-Lead MQFP or 196-Ball Mini-BGA Package
– 3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
– 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats
– 32-Bit Fixed-Point Data Format, Integer and Fractional, with Dual 80-Bit Accumulators
Parallel Computations
– Single-Cycle Multiply and ALU Operations in Parallel with Dual Memory Read/Writes and Instruction
Fetch
– Multiply with Add and Subtract for Accelerated FFT Butterfly Computation
– 1024-Point Complex FFT Benchmark: 0.274 ms (18,221 Cycles)
544 Kbits Configurable On-Chip SRAM
– Dual-Ported for Independent Access by Core Processor and DMA
– Configurable in Combinations of 16-, 32-, 48-Bit Data and Program Words in Block 0 and Block 1
DMA Controller
– Ten DMA Channels–Two Dedicated to the External Port and Eight Dedicated to the Serial Ports
– Background DMA Transfers at up to 66 MHz, in Parallel with Full Speed Processor Execution
– Performs Transfers Between:
Internal RAM and Host
Internal RAM and Serial Ports
Internal RAM and Master or Slave SHARC
Internal RAM and External Memory or I/O Devices
External Memory and External Devices
Host Processor Interface
– Efficient Interface to 8-, 16-, and 32-Bit Microprocessors
– Host Can Directly Read/Write ADSP-21065L IOP Registers