Inter-m GEQ-1231D, Руководство по обслуживанию

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Pin Type Function
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has
a 20kΩ internal pull-up resistor.
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDI has a 20kΩ internal pull-up resistor.
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-
21065L. TRST has a 20kΩ internal pull-up resistor.
EMU (O/D) O Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target
board connector only.
BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the
ADSP-21065L is current bus master of the shared external bus. The ADSP-
21065L drives BMSTR high only while it is the bus master. In a single-
processor system (ID=00), the processor drives this pin high.
CAS I/O/T SDRAM Column Access Strobe. Provides the column address. In
conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,
defines the operation for the SDRAM to perform.
RAS I/O/T SDRAM Row Access Strobe. Provides the row address. In conjunction with
CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation
for the SDRAM to perform.
SDWE I/O/T SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx and
sometimes SDA10, defines the operation for the SDRAM to perform.
DQM O/T SDRAM Data Mask. In write mode, DQM has a latency of zero and is used
to block write operations.
SDCLK
1-0
I/O/S/T SDRAM 2x Clock Output. In systems with multiple SDRAM devices
connected in parallel, supports the corresponding increased clock load
requirements, eliminating need of off-chip clock buffers. Either SDCLK
1
or
both SDCLKx pins can be three-stated.
SDCKE I/O/T SDRAM Clock Enable. Enables and disables the CLK signal. For details,
see the data sheet supplied with your SDRAM device.
SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with
a host access.
XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the
ADSP-21065L’s internal clock generator or to disable it to use an external
clock source. See CLKIN.
PWM_EVENT
1-0
I/O/A PWM Output/Event Capture. In PWMOUT mode, is an output pin and
functions as a timer counter. In WIDTH_CNT mode, is an input pin and
functions as a pulse counter/event capture.
VDD P Power Supply; nom3.3V dc. (33 pins)
GND G Power Supply Return. (37 pins)
NC Do Not Connect. Reserved pins that must be left open and unconnected. (7)
CLOCK SIGNALS
The ADSP-21065L can use an external clock or a crystal. See CLKIN pin description. You can configure the
ADSP-21065L to use its internal clock generator by connecting the necessary components to CLKIN and
XTAL. You can use either a crystal operating in the fundamental mode or a crystal operating at an overtone.
Figure shows the component connections used for a crystal operating in fundamental mode, and Figure 2
shows the component connections used for a crystal operating at an overtone.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE emulator uses the IEEE 1149.1 JTAG test access port of the ADSP-2106x to
monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-
2106x’s CLKIN, TMS, TCK, TRST, TDI, TDO, EMU and GND signals be made accessible on the target
system via a 14-pin connector (a 2 row x 7 pin strip header) such as that shown in Figure 3. The EZ-ICE
probe plugs directly onto this connector for chip-on-board emulation. You must add this connector to your
target board design if you, intend to use the ADSP-2106x EZ-ICE.
The total trace length between the EZ-ICE
connector and the furthest device sharing the EZ-
ICE JTAG pins should be limited to 15 inches
maximum for guaranteed operation. This restriction
on length must include EZ-ICE JTAG signals, which
are routed to one or more 2106x devices or to a
combination of 2106xs and other JTAG devices on
the chain.
The 14-pin, 2-row pin strip header is keyed at the
Pin 3 location–you must remove Pin 3 from the
header. The pins must be 0.025 inch square and at
least 0.20 inch in length. Pin spacing should be
0.1x0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
Figure 1. 30 MHz Operation (Fundamental Mode Crystal)
SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
ECLIPTEK EC2SM-33-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC-33-30.000M (THRU-HOLE PACKAGE)
C1=33pF
C2=27pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR
X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS.
Figure 2. 30 MHz Operation (3rd Overtone Crystal)
SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
ECLIPTEK EC2SM-T-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK ECT-30.000M (THRU-HOLE PACKAGE)
C1=18pF
C2=27pF
C3=75pF
L1=3300nH
Rs=SEE NOTE.
NOTE: C1, C2, C3, Rs AND L
1
ARE SPECIFIC TO CRYSTAL SPECIFIED
FOR X1.
CONTACT MANUFACTURER FOR DETAILS.
Figure 3. Target Board Connector for ADSP-2106x
EZ-ICE (JTAG Header)