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Basic Input Output System (BIOS)

SAI2 Server Board TPS

Revision

1.0

Beeps

Error

Cause

Recommended Action

2-3-1-3

All Memory Group Errors

Memory address signal failure

Change DIMM or M/B

3-3-1-4

Memory Not Detected

—

1-2

Option ROM Initialization Error

Failure to initialize Option ROM
BIOS

Change system board or option
board

1-2

Video configuration fails

Failure to initialize VGA BIOS

Change option video board or
system board

1-2

OPTION ROM Checksum Error

Failure to initialize Option BIOS

Change M/B or option board

3.7 Identifying BIOS Revision Level

The following sections provide information to help identify a system's current BIOS revision
level.

3.7.1

BIOS Revision Level Identification

During system POST, which runs automatically when the system is powered on, the monitor
displays several messages, one of which identifies the BIOS revision level currently loaded on
the system (see the following example).

Phoenix BIOS 4.0 Release 6.0.250A

In the example above, BIOS 6.0.250A is the current BIOS revision level loaded on the system.

Note

Press the

Esc

key to see the diagnostic messages.

Note:

The BIOS revision level

stated in the example might not reflect the actual BIOS setting in

any particular system.

Содержание SAI2

Страница 1: ...SAI2 Server Board Technical Product Specification Revision 1 0 November 2001 Enterprise Platforms and Services Marketing ...

Страница 2: ...Revision History SAI2 Server Board TPS Revision 1 0 ii Revision History Date Revision Number Modifications November 2001 1 0 Initial Release ...

Страница 3: ...l products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for confli...

Страница 4: ...ination Regulation Power 4 2 1 5 APIC Bus 4 2 1 6 Boxed Processors 4 2 2 ServerWorks ServerSet III LE Chipset 5 2 3 Memory 5 2 4 PCI I O Subsystem 6 2 4 1 64 bit 66 MHz PCI Subsystem 6 2 4 2 32 bit 33 MHz PCI Subsystem 6 2 5 Chipset Support Components 12 2 5 1 Legacy I O Super I O National PC87417 12 2 5 2 BIOS Flash 13 2 5 3 External Device Connectors 13 2 6 Interrupt Routing 13 2 6 1 Default I O...

Страница 5: ...2 POST Error Codes and Messages 42 3 7 Identifying BIOS Revision Level 44 3 7 1 BIOS Revision Level Identification 44 4 Jumpers and Connectors 45 4 1 SAI2 Server Board Jumper and Connector Locations 45 4 2 Jumper Blocks 47 4 2 1 Setting CMOS Password Clear Jumper Block JP5 47 4 3 Connectors 49 4 3 1 Main Power Connector ATX1 49 4 3 2 I2 C Connector J13 49 4 3 3 System Fan Connectors J8 J11 J7 J14 ...

Страница 6: ...ed Baseboard MTBF 59 6 2 Absolute Maximum Ratings 60 6 3 Calculated Power Consumption 60 6 4 Measured Power Consumption 61 7 Regulatory and Integration Information 62 7 1 Regulatory Compliance 62 7 2 Installation Instructions 63 7 2 1 Ensure EMC 63 7 2 2 Ensure Host Computer and Accessory Module Certifications 63 7 2 3 Prevent Power Supply Overload 64 7 2 4 Place Battery Marking on Computer 64 7 2...

Страница 7: ...ram 2 Figure 2 Embedded NIC PCI Signals 7 Figure 3 Video Controller PCI Signals 9 Figure 4 SAI2 Baseboard Interrupt Routing Diagram PIC Mode 15 Figure 5 SAI2 Baseboard Interrupt Routing Diagram Symmetric Mode 16 Figure 6 SAI2 Server Board Jumper and Connector Locations 45 Figure 7 I O Back Panel Connectors 46 ...

Страница 8: ...e 13 Peripheral Configuration Submenu Selections 27 Table 14 PCI Device Submenu Selections 28 Table 15 Option ROM Submenu Selections 28 Table 16 Numlock Submenu Selections 29 Table 17 Security Menu Selections 29 Table 18 Secure Mode Submenu Selections 30 Table 19 Server Menu Selections 30 Table 20 Wake On Events Submenu Selections 31 Table 21 Boot Device Priority Selections 31 Table 22 Hard Drive ...

Страница 9: ... 52 Table 41 Parallel Port Connector Pinout 52 Table 42 Serial Ports COM1 and COM2 Connector Pinouts 52 Table 43 RJ 45 LAN Connector Signals 53 Table 44 USB Connectors 53 Table 45 IDE Connector Pinout 53 Table 46 32 Bit PCI Connector Pinout 54 Table 47 64 Bit PCI Connctor Pinout 55 Table 48 Front Panel 24 pin Connector Pinout 56 Table 49 Estimated MTBF Calculated Numbers for SAI2 SC5100 59 Table 5...

Страница 10: ...List of Tables SAI2 Server Board TPS Revision 1 0 x This page intentionally left blank ...

Страница 11: ...odules VRM for support of both primary and secondary processors ServerWorks ServerSet III LE chipset 133 MHz Front Side Bus FSB Capability CNB30LE North Bridge CSB5 South Bridge Support for four 3 3 V registered ECC SDRAM DIMMs that are compliant with the JEDEC PC133 specification Support for DIMM sizes 64 MB to 1 GB Four DIMM slots allow a maxiumum installed memory of 4 GB ECC single bit correcti...

Страница 12: ...e following figure shows the major functional blocks of the SAI2 server board The following section describes the major components of the server board Figure 1 SAI2 Server Board Block Diagram SAI2 Server Board Block Diagram SAI2 Server Board Block Diagram 4x 32bit 33MHz PCI Slots Floppy Keyboard Mouse Serial Ports LPC Parallel Port Up to 4GB ECC Memory 4 DIMMs PC133 Buffered SDRAM PCI 32 33 2x 64b...

Страница 13: ... board is designed to accommodate one or two Intel Pentium III processors for the PGA370 socket The Pentium III processor for the PGA370 socket uses the same core and offers the same performance as the Intel Pentium III processor for the SC242 connector but utilizes a FC PGA This package utilizes the same 370 pin zero insertion force socket PGA370 used by the Intel Celeron processor 2 1 1 Supporte...

Страница 14: ...uth Bridge component 2 1 6 Boxed Processors The Intel Pentium III processor for the PGA370 socket is offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from a server board and standard components 2 1 6 1 Boxed Processor Fan Heatsinks The boxed Pentium III processor for the PGA370 socket will be supplied with an unattached fan heatsink t...

Страница 15: ...ridge The CSB5 South Bridge controller has several components It can be both a master and a target on the 32 bit 33 MHz PCI bus The CSB5 South Bridge also includes a USB controller and an IDE controller The CSB5 South Bridge is responsible for many of the power management functions with Advanced Configuration and Power Interface ACPI control registers built in The CSB5 South Bridge provides a numb...

Страница 16: ...CI segment includes two 64 bit 66 MHz 3 3 V keyed PCI expansion slots that can support 66 MHz 64 32 bit cards or 33 MHz 64 32 bit cards 64 bit PCI features include Bus speed up to 66 MHz 3 3 V signaling environment Burst transfers up to a peak of 528 MB per second MBps 8 16 32 or 64 bit data transfers Plug and Play ready Parity enabled 2 4 2 32 bit 33 MHz PCI Subsystem The 32 bit 33 MHz 5 V keyed ...

Страница 17: ...highly integrated PCI Local Area Network LAN controller for 10 or 100 Mbps Fast Ethernet networks As a PCI bus master the 82559 can burst data at up to 132 MBps This high performance bus master interface can eliminate the intermediate copy step in RX TX frame copies resulting in faster frame processing The network operating system communicates with the 82559 using a memory mapped I O interface PCI...

Страница 18: ... physical interface to TX magnetics The magnetics component terminates the 100Base TX connector interface A flash device stores the network ID Support for Wake on LAN WOL 2 4 2 2 Video Controller The SAI2 server board includes an ATI Rage XL video controller 8 MB video SDRAM and support circuitry for an embedded SVGA video subsystem The Rage XL 64 bit VGA Graphics Accelerator contains a SVGA video...

Страница 19: ...le 2 Video Controller Supported PCI Commands Rage XL Support C BE 3 0 _L Command Type Target Master 0000 Interrupt Acknowledge No No 0001 Special Cycle No No 0010 I O Read Yes No 0011 I O Write Yes No 0100 Reserved No No 0101 Reserved No No 0110 Memory Read Yes No 0111 Memory Write Yes No 1000 Reserved No No 1001 Reserved No No 1010 Configuration Read Yes No 1011 Configuration Write Yes No 1100 Me...

Страница 20: ...ler and power management controller Each function within the CSB5 South Bridge has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller sharing the same PCI bus interface On the SAI2 baseboard the primary role of the CSB5 South Bridge is to provide the gateway to all PC compatible I O devices and features The SAI2 server board uses the...

Страница 21: ...ps Buffering for PCI IDE burst transfers Master slave IDE mode Support for up to two devices per channel 2 4 2 3 3 USB Interface The CSB5 South Bridge contains a USB controller and USB hub The USB controller moves data between main memory and the two USB connectors provided The SAI2 server board provides a dual external USB connector interface Both ports function identically and with the same band...

Страница 22: ...mpatible with 16550A and 16450 modes and both are re locatable Each serial port can be set to one of four different COM x ports and each can be enabled separately When enabled each port can be programmed to generate edge or level sensitive interrupts When disabled serial port interrupts are available to add in cards 2 5 1 2 Parallel Port The SAI2 baseboard provides a 25 pin parallel port connector...

Страница 23: ...ST39SF040 is a high performance 4 megabit memory organized as 512K x8 bits in128 4 KB blocks The 8 bit flash memory provides 512K x 8 of BIOS and nonvolatile storage space The flash device is directly addressed as 8 bit ISA memory and accessed through the CSB5 X Bus interface 2 5 3 External Device Connectors The external I O connectors provide support for a PS 2 compatible mouse and keyboard an SV...

Страница 24: ... integrates a 16 entry I O APIC which is used to distribute 16 PCI interrupts 2 6 2 Extended I O APIC An additional 16 entry I O APIC is integrated in the CSB5 South Bridge to distribute EISA ISA interrupts This additional I O APIC is enabled only when the CSB5 South Bridge is configured to the Extended APIC configuration ...

Страница 25: ...RQ 10 IRQ 11 IRQ 12 IRQ 13 FERR IRQ 14 IRQ 15 CSB5 SCI D C B PCI1 1 PC87417 Super I O FERR IDE 0 IDE 1 PIRQ 0 PIRQ 1 PIRQ 2 PIRQ 3 PIRQ 4 PIRQ 5 PIRQ 6 PIRQ 7 PIRQ 8 PIRQ 9 PIRQ 10 PIRQ 11 PIRQ 12 PIRQ 13 PIRQ 14 PIRQ 15 PCI2 PCI3 PCI4 PCI5 PCI6 PCI IRQ to IRQ 1 setting by CSB5 I O Address C00h Interrupts Address Index Register and I O Address C01h Interrupt Redirection LAN VGA PCI 3 INT A PCI 4 I...

Страница 26: ... 7 IRQ 8 IRQ 9 IRQ 10 IRQ 11 IRQ 12 IRQ 13 FERR IRQ 14 IRQ 15 PIRQ0 16 PIRQ1 17 PIRQ2 18 PIRQ3 19 PIRQ4 20 PIRQ5 21 PIRQ6 22 PIRQ7 23 PIRQ8 24 PIRQ9 25 PIRQ10 26 PIRQ11 27 PIRQ12 28 PIRQ13 29 PIRQ14 30 PIRQ15 31 CSB5 Keyboard Serial Port2 Serial Port1 FDD Parallel Port RTC Mouse FERRL IDE 0 IDE 1 Timer Cascade PCI 1 PCI 2 PCI 3 PCI 4 PCI 5 PCI 6 LAN VGA PCI 3 INT A PCI 4 INT A PCI 2 INT A PCI 5 IN...

Страница 27: ...B30LE North Bridge from the default value 2 6 4 Relationship between PCI IRQ and PCI Device The relationship between PCI IRQ and PCI devices are defined as follows on the SAI2 server board Table 5 SAI2 Relationship between PCI IRQ and PCI Device PCI IRQ PCI Device PCI IRQ 0 PCI IRQ 1 PCI IRQ 2 Intel 82559 PCI IRQ 3 ATI Rage XL PCI IRQ 4 PCI Slot 3 INTA PCI IRQ 5 PCI Slot 4 INTA PCI IRQ 6 PCI IRQ 7...

Страница 28: ...is state The SAI2 server board supports sleep states s0 s1 s4 and s5 When the server board is operating in ACPI mode the operating system retains control of the system and the OS policy determines the entry methods and wake up sources for each sleep state sleep entry and wake up event capabilities are provided by the hardware but are enabled by the OS With future versions of Microsoft Windows 9X t...

Страница 29: ... The term BIOS as used in the context of this section refers to the system BIOS the BIOS Setup and option ROMs for on board peripheral devices that are contained in the system flash System BIOS controls basic system functionality using stored configuration values The terms flash ROM system flash and BIOS flash may be used interchangeably in this section The term BIOS Setup refers to the flash ROM ...

Страница 30: ...operational code located in the flash ROM A BIOS image is provided on a diskette in the form of a binary file that is read by the Phoenix Phlash Utility Baseboard revisions may create hardware incompatibilities and may require different BIOS code 3 1 2 1 System Flash ROM Layout The flash ROM contains system initialization routines BIOS strings BIOS Setup and run time support routines The exact lay...

Страница 31: ...ilities always update a checksum for both areas so that any potential data corruption is detectable by the BIOS before the hardware configuration takes place If data is corrupted the BIOS requests that the user reconfigure the system and reboot 3 2 2 Setup Utility Operation The ROM resident setup utility configures only on board devices The setup utility screen is divided into four functional area...

Страница 32: ...ut of any field This key will undo the pressing of the Enter key When the ESC key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the ESC key is pressed in any submenu the parent menu is re entered When the ESC key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded Selec...

Страница 33: ... user Main Menu Advanced Menu Security Menu System Menu Boot Menu Exit Menu These and associated submenus are described below 3 2 2 4 Main Menu Selections The following tables describe the available functions on the Main Menu and associated submenus Default values are highlighted Table 7 Main Menu Selections Feature Choices or Display Only Description User Setting Processor Type Display only Indic...

Страница 34: ...sure the disk is initialized by the BIOS before any accesses Primary Master Displays IDE device selection Enters submenu if selected Primary Slave Displays IDE device selection Enters submenu if selected Secondary Master Displays IDE device selection Enters submenu if selected Secondary Slave Displays IDE device selection Enters submenu if selected Table 8 Primary Secondary Master and Slave Adapte...

Страница 35: ... or Display Only Description User Setting Advanced Refer to Advanced Submenu Memory Reconfiguration Refer to Memory Reconfiguration Submenu CPU Reconfiguration Refer to CPU Reconfiguration Submenu Peripheral Configuration Refer to Peripheral Reconfiguration Submenu PCI Device Refer to PCI Device Submenu Option ROM Refer to Option ROM Submenu It Disables Enables the Option ROM BIOS on the PCI Bus N...

Страница 36: ...atus Display only Normal None Error DIMM Row Error Clears DIMM Errors Press Enter Clears the DIMM group error status information DIMM Error Pause Enabled Disabled If enabled the POST operation pauses if a DIMM error occurs Table 12 CPU Reconfiguration Submenu Selections Feature Choices or Display Only Description User Setting CPU 1 Status Display only Normal None Error CPU Error CPU 2 Status Displ...

Страница 37: ...rt 2 Parallel Port Disabled 378 IRQ5 378 IRQ7 278 IRQ5 278 IRQ7 3BC IRQ5 3BC IRQ7 Auto Disables the parallel port or selects the base address and interrupt IRQ for the Parallel port Parallel Mode Output only Bi directional EPP ECP DMA1 ECP DMA3 Selects the parallel port operation mode Diskette Controller Disabled Enabled Disables Enables the floppy disk controller Mouse Disabled Enabled Auto Detec...

Страница 38: ...eature Choices or Display Only Description User Setting Onboard LAN Enabled Disabled Disables Enables option ROM expansion for the on board LAN option ROM PCI Slot 1 Enabled Disabled Disables Enables the expansion of the option ROM for devices in PCI slot 1 PCI Slot 2 Enabled Disabled Disables Enables the expansion of the option ROM for devices in PCI slot 2 PCI Slot 3 Enabled Disabled Disables En...

Страница 39: ...n be disabled by setting it to a null string or by clearing password jumper on system board User Password is Display only Clear Once set this can be disabled by setting it to a null string or by clearing password jumper on system board Set Supervisor Password Press Enter Supervisor password controls access to the setup utility When the Enter key is pressed the user is prompted for a password press...

Страница 40: ...ours Period of keyboard and mouse inactivity before secure mode is activated and a password is required gain access Secure Mode HotKey Disabled Enabled Enables Disables the ability to lock the system with a CTRL ALT key combination The key can be selected and submenu appears when enabled A password is required to gain access Secure Mode Boot Disabled Enabled Enables Disables secure boot The system...

Страница 41: ...ity of the boot invocation Items can be re prioritized by using the up and down arrow keys to select the device Once the device is selected use the plus key to move the device higher in the boot priority list Use the minus key to move the device lower in the boot priority list Table 21 Boot Device Priority Selections Device Description User Setting ATAPI CD ROM Drive Attempts to boot from an ATAPI...

Страница 42: ...lt values for all Setup items Load Previous Value Read previous values of all Setup items from CMOS Save Changes Write all Setup item values to CMOS 3 3 CMOS Memory Definition Only the BIOS needs to know the CMOS map The CMOS map is available in the NVRAM LST file generated for every BIOS release The CMOS map is subject to change without notice 3 4 CMOS Default Override The BIOS detects the state ...

Страница 43: ... program such as Windows or EMM386 Phoenix Phlash uses the processor s flat addressing mode to update the flash part 3 5 1 Loading the System BIOS The BIOS update utility PHLASH loads a new copy of the BIOS into Flash ROM The loaded code and data include the following On board Video BIOS BIOS Setup Utility Quiet Boot Logo Area When running PHLASH in interactive mode the user may choose to update a...

Страница 44: ... code to help dealers create a user binary The user binary must adhere to the following requirements To allow detection by BIOS and protection from run time memory managers the user binary must have an option ROM header i e 55AAh size The system BIOS performs a scan of the user binary area at predefined points during POST Mask bits must be set within the user binary to inform the BIOS which entry ...

Страница 45: ... token that points to the reserved bits This token is of the following format MSB LSB 15 12 11 0 of bit available 1 Bit offset from start of CMOS of first bit The most significant four bits are equal to the number of CMOS bits available minus one This field is equal to seven since eight CMOS bits are available The 12 least significant bits define the position of the CMOS bit in the real time clock...

Страница 46: ...o initialization 04h Yes Yes This scan occurs immediately before video initialization 08h Yes No This scan occurs on POST error On entry BX contains the number of the POST error 10h Yes Yes This final scan occurs immediately prior to the INT 19 for normal boot and allows one to completely circumvent the normal INT 19 boot if desired 20h Yes Yes This scan occurs immediately before the normal option...

Страница 47: ...covery mode move the boot option jumper jumper block JP5 pins 9 10 to the recovery boot position By default and for normal operation pins 9 and 10 are not jumpered Recovery mode requires at least 8 MB of RAM in the first DIMM socket and drive A must be set up to support a 3 5 inch 1 44 MB floppy drive Note the system requires 64 MB to boot This is the mode of last resort used only when the main sy...

Страница 48: ...code is a series of individual beeps on the PC speaker each of equal length The following table describes the error conditions associated with each beep code and the corresponding POST checkpoint code as seen by a port 80h card For example if an error occurs at checkpoint 22h a beep code of 1 3 1 1 is generated The means there is a pause between the sequence that delimits the sequence Some POST co...

Страница 49: ...M 2C 1 3 4 1 Base RAM failure BIOS stops execution here if entire memory is bad 32 Test Processor bus clock frequency 34 Test CMOS 35 RAM Initialize alternate chipset registers 36 Warm start shut down 37 Reinitialize the chipset 38 Shadow system BIOS ROM 39 Reinitialize the cache 3A Autosize cache 3C Configure advanced chipset registers 3D Load alternate registers with CMOS values 40 Set Initial P...

Страница 50: ...g 7E Test coprocessor if present 82 Detect and install external RS232 ports 85 Initialize PC compatible PnP ISA devices 86 Re initialize on board I O ports 88 Initialize BIOS Data Area 8A Initialize Extended BIOS Data Area 8C Initialize floppy controller 90 Initialize hard disk controller 91 Initialize local bus hard disk controller 92 Jump to UserPatch2 93 Build MPTABLE for multi processor boards...

Страница 51: ...r D6 Initialize option ROM error D8 Shutdown error DA Extended Block Move DC Shutdown 10 error Table 29 Recovery BIOS Port 80 Codes CP Beeps Reason E0 Initialize chip set E1 Initialize bridge E2 Initialize processor E3 Initialize timer E4 Initialize system I O E5 Check forced recovery boot E6 Validate checksum E7 Go to BIOS E8 Initialize processors E9 Set 4 GB segment limits EA Perform platform in...

Страница 52: ...ess line Extended RAM failed Offset address 0233 Memory type mixing detected Memory type mixing detected 0234 Single bit ECC error Memory 1 bit error detected 0235 Multiple bit ECC error Memory multiple bit error detected 0250 System battery is dead Replace and run SETUP NVRAM battery dead 0251 System CMOS checksum bad Default configuration used CMOS checksum error 0252 Password checksum bad Passw...

Страница 53: ...ard resource is not mapped correctly N A System Configuration Data Write error System configuration data write error N A Warning IRQ not configured PCI interrupt is not configured correctly 8503 Incorrect memory speed in location XX XX Non PC133 DIMMs have been installed in slots XX XX A beep code is a series of individual beeps on the PC speaker each of equal length The following table describes ...

Страница 54: ...or option board 3 7 Identifying BIOS Revision Level The following sections provide information to help identify a system s current BIOS revision level 3 7 1 BIOS Revision Level Identification During system POST which runs automatically when the system is powered on the monitor displays several messages one of which identifies the BIOS revision level currently loaded on the system see the following...

Страница 55: ...ondary processor heat sink fan connector J9 B 66 MHz 64 bit PCI connectors M Floppy drive connector FDD C Primary processor connector CPU1 N Primary IDE connector PRI_IDE D Back panel connectors O Secondary IDE connector SEC_IDE E Primary processor heat sink fan connector J10 P Fan 3 connector J8 F Fan 5 connector J7 Q Fan 4 connector J11 G Fan 6 connector J14 R CSB5 South Bridge H Main power conn...

Страница 56: ... on the SAI2 server board I O panel OM12377 1 C B E F D G I A H ON Figure 7 I O Back Panel Connectors A Serial port 1 connector COM1 F Mouse connector B Serial port 2 connector COM2 G SVGA connector C NMI Non Maskable Interrupt switch H Network connector D Keyboard connector I USB connectors 2 E Parallel port connector ...

Страница 57: ...Numbers Function Jumper Position What it does at system reset 1 2 CMOS clear Open Protect Preserves the contents of CMOS Closed Erase Clears CMOS 3 4 Password protected Open Normal Preserves the password Closed Disable Disables the password 5 6 Reserved Open Not Used No function 7 8 Reserved Open Not Used No function 9 10 BIOS Recovery Boot Open Normal BIOS Recovery Boot disabled Normal operation ...

Страница 58: ...system press F2 at the prompt to run the BIOS Setup utility and select Get Default Values at the Exit menu 4 2 1 3 Perfoming a BIOS Recovery Boot In the event of BIOS corruption the following procedure may be used to perform a BIOS recovery 1 Obtain the BIOS update file package from Intel s http support intel com web site 2 A file called crisis zip is one of the files included with each SAI2 BIOS ...

Страница 59: ...r cord s and remove the chassis panel 12 Remove the BIOS recovery jumper from pins 9 10 and store the jumper on pins 11 12 13 Replace the chassis panel plug in the power cord s and power on the system 14 Perform a CMOS clear following the BIOS recovery 4 3 Connectors This section provides pin information about the connectors on the SAI2 server board 4 3 1 Main Power Connector ATX1 Table 33 Main Po...

Страница 60: ... Fan 6 Fan 6 J14 Table 35 Board Fan Connector Pinout Pin Signal 1 COM 2 PWM 3 Fan Sense 4 3 4 Processor Fan Connectors J10 J9 Primary Processor Fan 1 CPU1_FAN1 J10 Secondary Processor Fan 2 CPU2_FAN2 J9 Table 36 Processor Fan Connector Pinout Pin Signal 1 COM 2 12 VDC 3 Fan Sense 4 3 5 HDD LED J12 Table 37 HDD LED Pinout Pin Signal 1 N C 2 HDD LED Anode 3 HDD LED Anode 4 N C ...

Страница 61: ..._INDEX_L 9 GND 10 FD_MON0_L 11 GND 12 FD_SEL1_L 13 GND 14 FD_SEL0_L 15 GND 16 FD_MON1_L 17 GND 18 FD_DIR_L 19 GND 20 FD_STEP_L 21 GND 22 FD_WDATA_L 23 GND 24 FD_WGATE_L 25 GND 26 FD_TRK0_L 27 GND 28 FD_WPT_L 29 GND 30 FD_RDATA_L 31 GND 32 FD_SIDE_L 33 MSENO 2 34 1 33 34 FD_DCHG_L 4 3 7 SVGA Video Port VGA1 Table 39 Video Port Connector Pinout Pin Signal Pin Signal 1 Red 9 NC 2 Green 10 GND 3 Blue ...

Страница 62: ...T1 Table 41 Parallel Port Connector Pinout Pin Signal Pin Signal 1 STROBE_L 10 ACK_L 2 Data bit 0 11 Busy 3 Data bit 1 12 PE 4 Data bit 2 13 SLCT 5 Data bit 3 14 AUTO_L 6 Data bit 4 15 ERROR_L 7 Data bit 5 16 INIT_L 8 Data bit 6 17 SLCTIN_L 9 Data bit 7 18 25 GND 4 3 10 Serial Ports COM1 and COM2 Table 42 Serial Ports COM1 and COM2 Connector Pinouts Pin Signal Description 1 DCD Data carrier detect...

Страница 63: ... data stream received from the network 4 NC 5 NC 6 RX Receive data minus the negative signal for the RD differential pair contains the same input as pin 3 7 NC 8 NC 4 3 12 USB Connectors J2 Table 44 USB Connectors USB 1 Pin Signal USB 2 Pin Signal 1 5 VDC 1 5 VDC 2 USB_P1_N 2 USB_P0_N 3 USB_P1_P 3 USB_P0_P 4 GND 4 GND 4 3 13 IDE Connectors PRI_IDE SEC_IDE If no IDE drives are present no IDE cable ...

Страница 64: ...D B37 DEVSEL_L A7 INTC_L B7 INTB_L A38 STOP_L B38 GND A8 5 V B8 INTD_L A39 3 3 V B39 LOCK_L A9 Reserved B9 PRSNT1_L A40 SDONE B40 PERR_L A10 3 3 V B10 Reserved A41 SBO_L B41 3 3 V A11 Reserved B11 PRSNT2_L A42 GND B42 SERR_L A12 KEY B12 KEY A43 PARITY B43 3 3 V A13 KEY B13 KEY A44 AD15 B44 CBE1_L A14 3 3VSB B14 Reserved A45 3 3 V B45 AD14 A15 RST_L B15 GND A46 AD13 B46 GND A16 3 3 V B16 PCICLK A47...

Страница 65: ...D0 B58 AD1 A12 GND B12 GND A59 5 V B59 5 V A13 GND B13 GND A60 REQ64_L B60 ACK64_L A14 Reserved B14 Reserved A61 5 V B61 5 V A15 RST_L B15 GND A62 5 V B62 5 V A16 5 V B16 PCICLK A63 GND B63 Reserved A17 GNT_L B17 GND A64 CBE7_L B64 GND A18 GND B18 REQ_L A65 CBE5_L B65 CBE6_L A19 PME_L B19 5 V A66 3 3 V B66 CBE4_L A20 AD30 B20 AD31 A67 Parity B67 GND A21 3 3 V B21 AD29 A68 AD62 B68 AD63 A22 AD28 B2...

Страница 66: ... Reserved B92 Reserved A46 AD13 B46 GND A93 GND B93 Reserved A47 AD11 B47 AD12 A94 Reserved B94 GND 4 3 16 Front Panel 24 pin Connector Pinout FRONT_PANEL_HDR Table 48 Front Panel 24 pin Connector Pinout Pin Description 1 Power LED Anode 2 5VSB 3 Key 4 Reserved 5 Power LED Cathode 6 Reserved 7 Hard Drive Activity LED Anode 8 Reserved 9 Hard Drive Activity LED Cathode 10 Reserved 11 Power Switch Lo...

Страница 67: ...PU1 Monitors primary processor voltage CPU2 Monitors secondary processor voltage VCC3 Monitors VCC3 VCC Monitors VCC 12V Monitors 12V VTT Monitors VTT AGTL bus termination voltage 2 5V Monitors 2 5V 5VSB Monitors 5VSB 5V stand by Fan Speed CPU1_FAN Monitors primary processor fan speed CPU2_FAN Monitors secondary processor fan speed CHASSIS_FAN Monitors chassis fan speed through chassis fan header ...

Страница 68: ...Index 27h PKG Temperature VCOREA Index 20h CPU0 VRM VINR0 Index 21h CPU1 VRM 3 3VIN Index 22h 3 3V 5VIN Index 23h 5V 12VIN Index 24h 12V 12VIN Index 25h VTT 5VIN Index 26h 2 5V FAN1 divisor bit2 Index 5Dh Bank0 bit5 FAN1 divisor bt1 Index 47h bit5 FAN1 divisor bit0 Index 47h bit4 CPU0 FAN FAN1 Index 28h FAN2 divisor bit2 Index 5Dh Bank0 bit6 FAN2 divisor bt1 Index 47h bit7 FAN2 divisor bit0 Index ...

Страница 69: ...emperature 35 C Table 49 Estimated MTBF Calculated Numbers for SAI2 SC5100 Sub Assembly Description Sub Assy Qty Sub Assy MTBF Quote hrs Sub Assu Temp Quote C Sub Assy Duty Cycle Quote Duty Cycle as used in Sys Sub Assy temp in sys C Total Sub Assy MTBF hours Total Sub Assy Failure Rate FITs Baseboard 1 110 000 55 100 100 50 125 013 7 999 Front panel board typ 1 2 852 904 55 100 100 50 3 566 515 2...

Страница 70: ...n The following table shows the calculated power consumption for each of the power supply voltage rails for the SAI2 server board These values were calculated using the specifications for the on board components and processors Assumptions for add in card power and other peripherals powered from the server board are included in the table Customers will need to modify the calculated power consumptio...

Страница 71: ...s 6 4 Measured Power Consumption An SAI2 server board was configured with dual Pentium III 1 26GHz processors and four 1 GB PC133 SDRAM DIMMs The system was configured with Microsoft Windows 2000 Advanced Server Test software utilized during the power consumption measurement consisted of the Hipower test suite used to simulate medium processor activity and the WinMTA memory stress test suite used ...

Страница 72: ...patible Intel host system For information on Intel compatible host system s refer to Intel s Server Builder website or contact your local Intel representative Table 54 EMC Regulations Regulation Title FCC Class A Title 47 of the Code of Federal Regulations Parts 2 and 15 Subpart B pertaining to unintentional radiators USA ICES 003 Class A Interference Causing Equipment Standard Digital Apparatus C...

Страница 73: ...s or the instructions for associated modules contact the supplier s technical support to find out how to ensure that the system meets safety and regulatory requirements If the instructions are not followed the user increases safety risk and the possibility of noncompliance with regional laws and regulations 7 2 1 Ensure EMC Before computer integration the host chassis power supply and other module...

Страница 74: ...zed certification mark such as CSA or cUL signifies compliance with safety requirements No regulatory assessment is necessary for low voltage DC wiring used internally or wiring used externally when provided with appropriate overcurrent protection Appropriate protection is provided by a maximum 8 Amp current limiting circuit or a maximum approved 5 Amp fuse or positive temperature coefficient PTC ...

Страница 75: ...tion and testing of the board the user should observe all warnings and cautions in the installation instructions To avoid injury be aware of the following Sharp pins on connectors Sharp pins on printed circuit assemblies Rough edges and sharp corners on the chassis Hot components like processors voltage regulators and heat sinks Damage to wires that could cause a short circuit Observe all warnings...

Страница 76: ...Regulatory and Integration Information SAI2 Server Board TPS Revision 1 0 66 This page intentionally left blank ...

Страница 77: ...OS Data Area ECC Error Correcting Code EMP Emergency Management Port ESCD Extended System Configuration Data FC PGA Flip Chip Pin Grid Array FDC Floppy Disk Controller FIFO First In First Out FRB Fault Resilient Booting FRU Field Replaceable Unit FSB Front Side Bus ICH I O Controller Hub IDE Integrated Device Electronics I O Input Output IPMI Intelligent Platform Management Interface IPMB Intellig...

Страница 78: ...me Clock RX A communications abbreviation for receive Contrast with TX SCAM SCSI Configuration Automatically SDRAM Synchronous Dynamic Random Access Memory SDR Sensor Data Record SCSI Small Computer Systems Interface SE Single Ended SEL System Event Log SGRAM Synchronous Graphics RAM SIO Super I O SMC Satellite Management Controller SMI Server Management Interrupt SMM Server Management Module SSU ...

Страница 79: ...tion Revision 1 0 ATI Rage XL Technical Reference Manual I 2 C Bus Specification Intel 82559 Fast Ethernet Multifunction PCI CardBus Controller Datasheet PCI Local Bus Specification Revision 2 2 ServerWorks ServerSet III LE North Bridge Specification ServerWorks ServerSet III LE South Bridge Specification USB Specification Revision 1 0 VRM 8 4 DC DC Converter Specification Wired For Management Bas...

Страница 80: ... package 48 BitBLT engine 8 BMC 10 13 Board fan connector pinout 50 Boot Menu 21 23 31 Bridge 5 Burst transfers 6 Bus speed 6 C Certification 63 Chained memory structure 8 Checksum error 37 CMOS 12 13 19 20 21 34 35 49 CMOS clear 32 47 48 CMOS clear jumper 21 CMOS map 32 CNB30LE T 1 5 17 Configuration 21 23 25 32 Connector PCI 60 Console Redirection 20 Controller 7 crisdisk bat 37 48 crisis zip 48...

Страница 81: ...uration 25 Memory Write 9 Mouse connector 46 MPS 20 25 MTBF 59 I Multi Processor Specification 20 N Network connector 46 NMI switch 46 North Bridge 1 5 17 NVRAM 21 32 NVRAM LST 32 P Parallel port connector 46 Parallel port connector pinout 52 Password Change 47 Disable jumper 47 Password Clear 47 Password disable jumper 48 Password settings 32 PC87417 2 12 13 PCI IDs 17 PERR 54 PGA370 1 3 4 Phlash...

Страница 82: ...C 11 PNP 13 Power management controller 11 USB 1 11 SST39SF040 13 Super I O Controller 2 Supervisor 29 SVGA connector 46 System initialization routines 20 System Menu 21 23 System Setup Utility 21 System Setup Utility 19 T termination circuitry 4 Transfer Mode 25 TX magnetics 8 U Ultra DMA Mode 11 Universal Serial Bus 60 USB 60 USB connections 13 USB connectors 11 46 53 USB controller 5 6 10 11 28...

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