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Intel S5500WB Скачать руководство пользователя страница 98

Power Subsystem

Intel® Server Board S5500WB TPS

Revision 1.9

Intel order number E53971-008

84

The SSI uses the standard 24-pin and 8-pin power headers along with the 5pin Control
connector. The 12-V only uses two 8-pin power headers, a 7-pin control header and a 6 pin
HDD power connector. For maximum rack server efficiency, a DC 12-V only power supply is
recommended. Appendix A shows connector pin outs.

PMbus communications between the power supply and server board must comply with both
SMBus and I2C Bus timing requirements.

10.3

Power Sequencing and Reset Distribution

The IBMC device is integrated into the power control and reset logic of the system. This design
reduces the discrete logic requirements of previous generations and at the same time permits
FW to manage certain features related to the power on/off control and the reset logic.

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Содержание S5500WB

Страница 1: ...Intel Server Board S5500WB Technical Product Specification Intel order number E53971 008 Revision 1 9 February 2012 Enterprise Platforms and Services Division ...

Страница 2: ...ure 08 03 2009 1 3 Updated memory support Corrected PCIe slot speed Removed S4 support 01 12 2010 1 4 Corrected USB header pin out 03 09 2010 1 5 Updated Power Supply communication bus requirements Increased maximum supported memory to 128GB Added support for 5600 series processors 04 21 2010 1 6 Updated12V SKU board picture Figure 1 07 18 2010 1 7 Removed Rapid Boot Toolkit section Updated NIC LE...

Страница 3: ...ntains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design This document may contain design defects or errors known as errata which may cause the product to deviate from published ...

Страница 4: ...or Subsystem 15 3 3 1 Processor Support 15 3 3 2 Processor Population Rules 15 3 3 3 Installing or Replacing the Processor 17 3 3 4 Intel QuickPath Interconnect Intel QPI 20 3 4 Intel QuickPath Memory Controller 21 3 4 1 Supported Memory 21 3 4 2 Memory Subsystem Nomenclature 21 3 4 3 ECC Support 22 3 4 4 Memory Reservation for Memory mapped Functions 22 3 4 5 High Memory Reclaim 22 3 4 6 Memory P...

Страница 5: ...deo 35 3 12 3 Front Panel Video 35 3 13 I O Slots 36 3 13 1 X16 Riser Slot Definition 36 3 13 2 PE WIDTH Strapping 36 3 13 3 Slot 1 PCI Express x8 Connector 36 3 13 4 I O Module Connector 37 4 Intel I O Expansion Modules 38 5 Platform Management Features 40 5 1 BIOS Feature Overview 40 5 1 1 EFI Support 40 5 1 2 BIOS Recovery 40 5 2 BMC Feature Overview 40 5 2 1 Server Engines Pilot II Controller ...

Страница 6: ...2 51 7 Connector Header Locations and Pin out 52 7 1 Power Connectors 52 7 2 System Management Headers 54 7 2 1 Intel Remote Management Module 3 Intel RMM3 Connector 54 7 2 2 BMC Power Cycle Header 12V Only 54 7 2 3 Hard Drive Activity Input LED Header 55 7 2 4 IPMB Header 55 7 2 5 SGPIO Header 55 7 3 SSI Control Panel Connector 55 7 3 1 Power Button 56 7 3 2 Reset Button 56 7 3 3 NMI Button 56 7 ...

Страница 7: ...e Sensor 78 9 2 2 Memory Temperature Sensor 79 9 2 3 Board Temperature Sensor 79 9 2 4 Thermals Sensor Placement 79 9 3 Heatsinks 80 9 3 1 Unified Retention System Support 81 9 4 Errors 82 9 4 1 PROCHOT 82 9 4 2 THERMTRIP 82 9 4 3 CATERR 82 10 Power Subsystem 83 10 1 Server Board Power Distribution 83 10 2 Power Supply Compatibility 83 10 3 Power Sequencing and Reset Distribution 84 11 Regulatory ...

Страница 8: ... E53971 008 viii 11 3 1 FCC Verification Statement USA 86 11 3 2 ICES 003 Canada 87 11 3 3 Europe CE Declaration of Conformity 88 11 3 4 BSMI Taiwan 88 11 3 5 KCC Korea 88 Appendix A POST Code LED Decoder 89 Appendix B Video POST Code Errors 96 Glossary 100 Reference Documents 103 ...

Страница 9: ...gure 12 Installing processor 18 Figure 13 Package Installation Remove Feature 19 Figure 14 Installing Removing Heatsink 20 Figure 15 Intel QPI Link 20 Figure 16 Memory Channel Population 23 Figure 17 Installing Memory 24 Figure 18 Mirroring Memory Configuration 26 Figure 19 Integrated BMC Hardware 33 Figure 20 S5500WB I2C SMBUS Block Diagram 44 Figure 21 Jumper Blocks J1B5 J1C2 J1C3 J1B4 J6A3 J6A2...

Страница 10: ...List of Figures Intel Server Board S5500WB TPS Revision 1 9 Intel order number E53971 008 x Figure 32 Power Distribution Diagram 83 Figure 33 Diagnostic LED Placement Diagram 89 ...

Страница 11: ...anced Features 42 Table 16 I2C SMBus Device Address Assignment 44 Table 17 Server Board Jumpers J1B5 J1C2 J1C3 J1B4 J6A3 J6A2 47 Table 18 Force IBMC Update Jumper 47 Table 19 Password Clear Jumper 48 Table 20 BIOS Recovery Mode Jumper 49 Table 21 Reset BIOS Jumper 50 Table 22 Video Master Jumper 50 Table 23 SSI SKU 24 pin 2x12 Connector J9B3 52 Table 24 CPU 12V Power 2x4 Connector J5K1 52 Table 25...

Страница 12: ...n Module Connector Pin out J2B1 J3B1 65 Table 44 External RJ 45 Serial Port A COM1 J7A1 66 Table 45 Internal 9 pin Serial B COM2 J1A2 66 Table 46 External USB Connector J8A1 J9A1 66 Table 47 Internal USB Connector J1C1 and J9A2 66 Table 48 Low Profile Internal USB Connector J1E3 67 Table 49 SSI 4 pin Fan Connector J2K2 J2K3 J3K1 J7K1 J8K4 J8K5 67 Table 50 8 pin Fan Connector J2K1 J8K3 MOLEX CONNEC...

Страница 13: ...Intel Server Board S5500WB TPS List of Tables Revision 1 9 Intel order number E53971 008 xiii This page is intentionally left blank ...

Страница 14: ......

Страница 15: ...ction 11 Regulatory and Certification Information Appendix A POST Code LED Decoder Appendix B Video POST Code Errors Glossary Reference Documents 1 2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server bu...

Страница 16: ...ion VRD optimized to support QR x8 DIMMs No support for QR x4 DIMMs Chipset Intel 5500 Chipset IOH Intel 82801Jx I O Controller Hub ICH10R I O Control External connections DB 15 Video connectors RJ 45 serial Port A connector RJ 45 connector for 10 100 1000 LAN One 2x USB 2 0 connectors One RJ 45 over USB for 10 100 1000 LAN Internal connections Two USB 2x5 pin header supporting four USB 2 0 ports ...

Страница 17: ...e wide I O modules Video Onboard ServerEngines LLC Pilot II Controller Matrox G200 2D Video Graphics controller Uses 8 MB of the BMC 32 MB DDR2 Memory Hard Drive Support for six ICH10R SATA II ports Optional support for SW RAID 5 with activation key LAN Two 10 100 1000 ports provided by Intel 82576 PHYs with Intel I O Acceleration Technology 2 support Server Management Onboard ServerEngines LLC Pi...

Страница 18: ...Revision 1 9 Intel order number E53971 008 2 1 Intel Server Board S5500WB Server Board The Intel Server Board S5500WB has two board SKUs such as SSI compliant and 12 V only SKU The board layouts of the SKUs are shown Figure 1 Intel Server Board S5500WB 12V ...

Страница 19: ...Intel Server Board S5500WB TPS Server Board Overview Revision 1 9 Intel order number E53971 008 5 Figure 2 Intel Server Board S5500WB SSI ...

Страница 20: ...r Board Overview Intel Server Board S5500WB TPS 6 Revision 1 9 Intel order number E53971 008 2 2 Server Board Connector and Component Layout Figure 3 Intel Server Board S5500WB Components both SKUs are shown ...

Страница 21: ...nector MEM2 G Battery BB 8 pin Fan Connector MEM2R H SATA Connectors CC DIMM Slot D2 I 24 Pin Connector SSI only DD DIMM Slot D1 J 8 Pin Connector 12V only EE DIMM Slot E1 K Aux Power 5 pin or 7 pin FF DIMM Slot F1 L RAID Key GG Front Panel Connector M DIMM Slot C1 HH HDD LED Header N DIMM Slot B1 II Low Profile USB Connector O DIMM Slot A1 JJ Internal VGA Connector P DIMM Slot A2 KK BMC Power Cyc...

Страница 22: ...wing board rear connector placement Figure 4 Rear Panel Connector Placement Description Description A ID LED E RJ 45 GbE LAN connector B Status LED F RJ 45 Serial port connector C RJ 45 GbE Dual USB connector G DB15 Video D Dual USB connector H Diagnostic LEDs 2 2 2 Server Board Mechanical Drawings The following figures are mechanical drawings for the Intel Server Board S5500WB ...

Страница 23: ...Intel Server Board S5500WB TPS Server Board Overview Revision 1 9 Intel order number E53971 008 9 Figure 5 Baseboard and Mounting holes ...

Страница 24: ...Server Board Overview Intel Server Board S5500WB TPS 10 Revision 1 9 Intel order number E53971 008 Figure 6 Connector Locations ...

Страница 25: ...Intel Server Board S5500WB TPS Server Board Overview Revision 1 9 Intel order number E53971 008 11 Figure 7 Primary Side Height Restrictions ...

Страница 26: ...Server Board Overview Intel Server Board S5500WB TPS 12 Revision 1 9 Intel order number E53971 008 Figure 8 Secondary Side Height Restrictions ...

Страница 27: ...ocket B B Chipset Intel 5500 Chipset IOH Intel 82801Jx I O Controller Hub ICH10R Intel 5500 Chipset IOH Intel 82801Jx I O Controller Hub ICH10R Memory 8 RDIMMs or 8 UDIMMs DDR3 8 RDIMMs or 8 UDIMMs DDR3 Slots 1 PCI Express x8 w x16 connector 1 PCI Express x4 w x8 connector 1 PCI Express x8 w x16 connector 1 PCI Express x4 w x8 connector Ethernet Dual GbE Intel 82576 Gigabit Ethernet Dual GbE Intel...

Страница 28: ...Functional Architecture Intel Server Board S5500WB TPS 14 Revision 1 9 Intel order number E53971 008 3 2 Functional Block Diagram Figure 9 Intel Server Board S5500WB Functional Block Diagram ...

Страница 29: ...ket B package with 4 8 GT s 5 86 GT s or 6 4 GT s Intel QPI Up to 95 W Thermal Design Power TDP Supports Low Voltage LV processors 3 3 2 Processor Population Rules For optimum performance when two processors are installed both must be the identical revision and have the same core voltage and Intel QPI core speed When only one processor is installed it must be in the socket labeled CPU1 The other s...

Страница 30: ...enominator Continues to boot the system successfully If the frequencies for all processors cannot be adjusted to be the same then the BIOS Logs the error into the SEL Displays 0197 Processor speeds mismatched message in the error manager Halts the system Processor microcode missing Minor The BIOS detects the error condition and responds as follows Logs the error into the SEL Does not disable the p...

Страница 31: ...move the server s cover See the document that came with your server chassis for instructions on removing the server s cover 5 Locate the processor socket and raise the raise the load lever of the ILM cover completely see letter A in the figure below Figure 10 Lifting the load lever of ILM cover 6 Open the load plate see letter B in Figure 10 and letter C in Figure 11 Figure 11 Removing the socket ...

Страница 32: ...ent with the socket A The package Pin1 triangle and the socket Pin1 chamfer provide a visual reference for proper orientation B The package substrate has orientation notches along two opposing edges of the package offset from the centerline The socket has two corresponding orientation posts to physically prevent mis orientation of the package These orientation features also provide an initial roug...

Страница 33: ...airflow through the system 3 Set the heatsink over the processor lining up the four captive screws with the four posts surrounding the processor 4 Loosely screw in the captive screws on the heatsink corners in a diagonal manner according to the numbers shown in as follows a Starting with the screw at location 1 engage the screw threads by giving it two rotations in the clockwise direction and stop...

Страница 34: ...l QuickPath Interconnect Intel QPI Intel QPI is a cache coherent link based interconnect specification for processor chipset and I O bridge components You can use it in a wide variety of desktop mobile and server platforms spanning IA 32 and Intel Itanium architectures Intel QPI also provides support for high performance I O transfer between I O nodes It allows connection to standard I O buses suc...

Страница 35: ...with two DIMMs on the first channel and one DIMM on the second and third channels of each processor Therefore the server board supports up to 8 DIMMs with dual processor sockets with a maximum memory capacity of 128 GB The server board supports DDR3 800 DDR3 1067 and DDR3 1333 memory technologies Memory modules of mixed speed are supported by automatic selection of the highest common frequency of ...

Страница 36: ...CC Support If at least one non ECC DIMM is present in the system the system reverts to non ECC mode UDIMMs can be ECC or non ECC RDIMMs are always ECC enabled Non ECC DIMMs are not validated and not recommended for server use 3 4 4 Memory Reservation for Memory mapped Functions A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset processor and BIOS flash memory mapped...

Страница 37: ...fore if A1 is empty you cannot populate use A2 Figure 16 Memory Channel Population 3 4 7 Installing and Removing Memory The silkscreen on the board next to CPU1 displays DIMM_A2 DIMM_A1 DIMM_B1 DIMM_C1 and next to CPU2 display DIMM_D2 DIMM_D1 DIMM_E1 DIMM_F1 starting from the inside of the board DIMM_A1 is the blue socket closest to the CPU 1 socket For memory channel A the server board requires D...

Страница 38: ...ted push down on the top edge of the DIMM until the retaining clips snap into place letter D in Figure 16 Make sure the clips are firmly in place letter E in Figure 16 9 Replace the server s cover and reconnect the AC power cord 3 4 7 2 Removing DIMMs To remove a DIMM follow these steps 1 Turn off all peripheral devices connected to the server 2 Turn off the server 3 Remove the AC power cord from ...

Страница 39: ...nnels A and B must have DIMMS of identical parameters If one socket fails the population requirements for RAS the BIOS sets all six channels to the Independent Channel mode One exception to this rule is when all DIMM slots from a socket are empty for example when only DIMM slots A1 B1 and C1 are populated mirroring is possible on the platform 3 4 9 1 Memory Population for Channel Mirroring Mode Th...

Страница 40: ...a path to the legacy bridge In addition the Intel 5500 Chipset supports a x4 DMI Direct Media Interface link interface for the legacy bridge and interfaces with other devices through SMBus Controller Link and RMII Reduced Media Independent Interface manageability interfaces The Intel 5500 Chipset supports the following features and technologies Intel QuickPath Interconnect Intel QPI PCI Express Ge...

Страница 41: ...s directly into the CPU cache through hints to the processor to perform a data pre fetch and install it in its local caches The Intel 5500 series and 5600 series processor supports Direct Cache Access DCA You enable or disable DCA in the BIOS processor setup menu 3 5 1 2 Intel Virtualization Technology for Directed I O Intel VT d The Intel Virtualization Technology is designed to support multiple ...

Страница 42: ... commands Use of this capability on Intel servers is platform SKU specific o ICH10 temperature monitoring PECI 2 0 Proxy SPS offers a means for a BMC without a PECI 2 0 interface to use the ME as a PECI proxy The BMC on Intel servers already has a PECI 2 0 interface so this SPS capability is not used 3 7 Intel 82801Jx I O Controller Hub ICH10R The Intel 82801Jx I O Controller Hub ICH10R provides e...

Страница 43: ...e RAID 5 pack Intel Embedded Server RAID Technology functionality requires the following items ICH10R IO Controller Hub Software RAID option is selected on BIOS menu for SATA controller Intel Embedded Server RAID Technology II Option ROM Intel Embedded Server RAID Technology II drivers most recent revision At least two SATA hard disk drives 3 7 1 2 Intel Embedded Server RAID Technology II Option R...

Страница 44: ...ain standby voltage rail via DC to DC Voltage regulators for efficiency purposes It is on standby power so the BMC can send out of band management traffic over the RMII bus to the network during sleep state S5 The NIC supports the normal RJ 45 LINK Activity speed LEDs as well as the Proset ID function These LEDs are powered from a Standby voltage rail The link activity LED at the right of the conn...

Страница 45: ...ement Controller The ServerEngines LLC Pilot II Integrated BMC is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI based server management Firmware usage of these hardware features is platform dependant The following is a summary of the Integrated BMC management hardware features used by the ServerEngines LLC Pilot II Integrated BMC IPMI 2 0...

Страница 46: ...S support SMI and PME support ACPI compliant Wake up control The Pilot II contains an integrated KVMS subsystem and graphics controller with the following features USB 2 0 for keyboard mouse and storage devices Hardware Video Compression for text and graphics Hardware encryption 2D Graphics Acceleration DDR2 graphics memory interface Matrox 2000 Graphics core with PCI Express x1 host interface Up ...

Страница 47: ...ludes two dedicated 10 100 network interfaces These interfaces are not shared with the host system At any time you can enable only one dedicated interface for management traffic The default active interface is the NIC 1 port For these channels you can enable support for IPMI over LAN and DHCP For security reasons embedded LAN channels have the following default settings IP Address Static All users...

Страница 48: ...LDAP Support 3 10 Serial Ports The server board provides two serial ports an external RJ 45 serial port and an internal serial header The rear RJ 45 serial A port is a fully functional serial port that can support any standard serial device The serial B port is an optional port that is accessed through a 9 pin internal DH 10 header You can use a standard DH 10 to DB9 cable to direct serial A port ...

Страница 49: ... the BIOS In the single mode dual monitor video disabled the onboard video controller is disabled when an add in video card is detected In the dual mode onboard video enabled dual monitor video enabled the onboard video controller is enabled and is the primary video device The external video card is allocated resources and is considered the secondary video device The BIOS Setup utility provides op...

Страница 50: ... using a taller riser and extending the board over the 1U CPU heatsinks or if CPU2 is unpopulated Appendix A describes the pin assignments for this connector 3 13 2 PE WIDTH Strapping On the Intel Server Board S5500WB the IOH needs to be informed of the PCI Express bus width during power on This is accomplished using the PEWIDTH input straps The mechanism used is the PEWIDTH bits one bit is used t...

Страница 51: ...S5000PAL and newer double wide Gen 2 I O modules supported by the Intel Server Board S5520UR are supported on the Intel Server Board S5500WB The Intel I O Expansion Module is also required to inform the IOH of the Intel I O Expansion Module Bus usage PEWIDTH bit 1 is to be used for this Table 12 Intel I O Expansion Module Bus PEWIDTH Bits Intel I O Expansion Module Description PEWIDTH1 Pin 2 one x...

Страница 52: ...O Expansion Module controller does not support a single wide module it is only used to support a double wide module You must mount single wide modules on connector J3B1 closest to Slot 6 marked Legacy Intel I O Expansion Module on the silkscreen When double wide Intel I O Expansion Modules are installed there might be interference with some adapters installed in Slot 1 The following table shows th...

Страница 53: ...roduct Code Description AXX4GBIOMOD2 Quad port Gigabit Ethernet I O Expansion Module based on the Intel 82576EB Gigabit Ethernet Controller AXXIBQDRMOD InfiniBand I O Expansion Module Single Port QDR For more information refer to the I O modules in the Intel I O Expansion Modules Hardware Specification ...

Страница 54: ...POST through a GPIO and if set defaults to a recovery mode of operation that allows restoration of the BIOS Flash to a full operational state The platform BIOS supports a Reset BIOS Configuration Jumper The BIOS samples this jumper during POST through a GPIO and if set resets its configuration information stored in Flash memory 5 2 BMC Feature Overview The server management subsystem consists of m...

Страница 55: ...es to transfer large blocks of data up to 32 K much faster than KCS can IPMI commands are embedded in data written read to a virtual CD ROM device The embedded server management firmware stack is based on a core stack from American Megatrends Incorporated AMI The stack runs on an embedded version of the Linux operating system and provides support for current industry standard management interfaces...

Страница 56: ...Server Engines PILOT II integrated BMC to offer a dedicated management Ethernet port Table 15 Advanced Features Manageability features Description Embedded Web UI Remote Power on off sensor status system info System Event log OEM customization KVM Redirection high performance multiple concurrent sessions USB 2 0 Media Redirection boot over remote media Security SSL SSH support WS MAN Dedicated NIC...

Страница 57: ...ta centers This includes capabilities such as secure power and reset control temperature monitoring event logging and others For more information refer to www intel com go dcmi 5 5 Other Platform Management The platform supports the following sleep states S1 and S5 Within S0 the platform supports additional lower power states such as C1e and C6 for the CPU 5 5 1 Wake On LAN WOL Wake On LAN WOL is ...

Страница 58: ...ent Main Bus Power Rail Sub Bus Power Rail Device I2C SMBus Address Note Host 3V3SB NA NA IBMC I2C SMBus 3 No Connect ICH10R SMBus 0x88 CK509B 0xD2 DB403 0xDC Host 3V3 XDP DB803 0xDC CPU0 DIMM 1A 0xA0 CPU0 DIMM 2A 0xA2 CPU0 DIMM 1B 0xA4 CPU0 DIMM 1C 0xA6 CPU0 DIMM 1D 0xA8 CPU0 DIMM 2D 0xAA CPU0 DIMM 1E 0xAC CPU0 DIMM 1F 0xAE Sensor 3V3SB NA NA IBMC I2C SMBus 1 Temp Sensor 0x9E FP Temp Sensor 0x9A ...

Страница 59: ...53971 008 45 Main Bus Power Rail Sub Bus Power Rail Device I2C SMBus Address Note LAN 3V3SB NA NA IBMC I2C SMBus 5 NIC LAN Link 3V3SB NA NA IBMC I2C SMBus 4 ICH10R SMLINK 0x88 PWR 5V PS FRU 0xAC PS I2C PSMI 0xB0 Spare 3V3SB NA NA IBMC I2C SMBus 2 DDC 3V3SB DDC 5V IBMC GFX DDC Video Monitor 0xA0 ...

Страница 60: ...owing table provides a summary and description of configuration test and debug jumpers on the Intel Server Board S5500WB The server board has several 3 pin jumper blocks that can be used Pin 1 on each jumper block can be identified by the following symbol on the silkscreen Figure 21 Jumper Blocks J1B5 J1C2 J1C3 J1B4 J6A3 J6A2 J7A2 ...

Страница 61: ... 2 Disabled Default 2 3 Enabled J6A2 Serial Interface 1 2 DCD to DTR Data Carrier Detect 3 4 DSR to DTR Data Set Ready 6 1 1 Force IBMC Update J1B5 When performing a standard BMC firmware update procedure the update utility places the BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event the BMC firmware update process fails due to the BMC not bei...

Страница 62: ...ess fails This jumper should remain in the default disabled position when the server is running normally The server board has several 3 pin jumper blocks that can be used to configure protect or recover specific features of the server board 6 1 2 Password Clear J1C2 The user sets this 3 pin jumper to clear the password Table 19 Password Clear Jumper Jumper Position Mode of Operation Note 1 2 Norma...

Страница 63: ...sk This process takes place before any video or console is available Once the system boots to this recovery image file FVMAIN FV it boots automatically into the EFI Shell to invoke the Startup nsh script and start the flash update application IFlash32 efi IFlash32 efi requires the supporting BIOS Capsule image file Rec CAP After the update is complete a message displays stating the BIOS has been u...

Страница 64: ...r back to default position covering pins 1 and 2 7 Close the server chassis 8 Power up the server The CMOS is now cleared and you can reset it by going into the BIOS setup Note Removing AC Power before performing the CMOS Clear operation causes the system to automatically power up and immediately power down after the procedure is followed and AC power is re applied If this happens remove the AC po...

Страница 65: ...boot the recovery loader is started first and it tries to load the active firmware image by running the loader of this image If it fails to boot it tries to boot the other operational image If both fail the recovery loader starts in recovery mode The recovery mode can also be forced setting the MGPIOx jumper on the board Boot image verification and boot failure 6 1 7 Serial Interface J6A2 Pins Mod...

Страница 66: ...B3 Pin Signal Name Pin Signal Name 1 3 3V 13 3 3V 2 3 3V 14 12V 3 GND 15 GND 4 5V 16 PS_ON 5 GND 17 GND 6 5V 18 GND 7 GND 19 GND 8 PWR_GD 20 NC 9 SB5V 21 5V 10 12V 22 5V 11 12V 23 5V 12 3 3V 24 GND Table 24 CPU 12V Power 2x4 Connector J5K1 Pin Signal Name 1 GND 2 GND 3 GND 4 GND 5 12V 6 12V 7 12V 8 12V Table 25 SSI Power Control J9D1 Pin Signal Name 1 SMB_PWR_CLK 2 SMB_PWR_DAT 3 SMB_PWR_ALRT 4 GND...

Страница 67: ...CONN ELECTRONICS INC HF1107V P1 or TYCO ELECTRONICS CORPORATION 5 104809 6 Pin Signal Name 1 SMB_PWR_CLK 2 SMB_PWR_DAT 3 SMB_PWR_ALRT 4 Remote Sense Return 5 12V Remote Sense 6 PS_ON 7 5V S B Table 28 Peripheral Power Only for 12 V only SKU J8K2 iPN C22293 003 MOLEX CONNECTOR CORPORATION 43045 0627 Note This connector is for output power only The 5V is limited to 6 5A and the 3 3V is limited to 2A...

Страница 68: ...dule Intel RMM or the Intel Remote Management Module 2 Intel RMM2 Table 29 Intel RMM3 Connector Pin out J5B1 7 2 2 BMC Power Cycle Header 12V Only A header is provided so you can use an external switch to remove power from the BMC In effect it causes a BMC Power on reset to occur Table 30 BMC Power Cycle Header J1D2 Pin Description Note 1 RST_BMC_PWR_CYC When power is removed from the BMC 2 GND If...

Страница 69: ... Data Out 4 SDOUT1 SGPIO Data In 7 3 SSI Control Panel Connector The server board provides a 24 pin SSI front panel connector J1E2 for use with SSI compliant third party chassis The following table provides the pin out for this connector Table 33 Front Panel SSI Standard 24 pin Connector Pin out J1E2 Pin Signal Name Pin Signal Name 1 P3V3_STBY Power LED Anode 2 P3V3_STBY Front Panel Power 3 Key 4 ...

Страница 70: ...ated BMC monitors power state signals from the chipset and de asserts PS_PWR_ON to the power supply As a safety mechanism if the BIOS fails to service the request the Integrated BMC automatically powers off the system in four to five seconds Power Button On to Off operating system present If an ACPI operating system is running pressing the power button switch generates a request via SCI to the ope...

Страница 71: ...e and a non critical fault due to another source the system status LED state would be solid on the critical fault state The system status LED is a bicolor LED Green status shows a normal operation state or a degraded operation Amber fault shows the system hardware state and overrides the green status The Integrated BMC detected state and the state from the other controllers such as the SCSI SATA h...

Страница 72: ...stem has redundant power supplies Amber 1 Hz blink Non Fatal Non fatal alarm system is likely to fail BIOS Detected 1 In non mirroring mode if the threshold of ten correctable errors is crossed within the window 1 2 PCI Express uncorrectable link errors Integrated BMC Detected 3 Critical threshold crossed Voltage temperature power nozzle power gauge and PROCHOT therm Ctrl sensors 4 VRD Hot asserte...

Страница 73: ...hassis ID button is pressed then the chassis ID LED changes to solid on If the button is pressed again with no intervening commands the chassis ID LED turns off 7 4 I O Connectors 7 4 1 PCI Express Connectors The Intel Server Board S5500WB has two PCI Express slots The pin outs for the slots are shown in the following tables Table 37 Slot 6 Riser Connector J4B1 Pin Side B PCI Express Signal PCI Ex...

Страница 74: ...ND PERxN2 26 68 GND PERxP12 68 27 PETxP3 GND 27 69 GND PERxN12 69 28 PETxN3 GND 28 70 PETxP13 GND 70 29 GND PERxP3 29 71 PETxN13 GND 71 30 RSVD PERxN3 30 72 GND PERxP13 72 31 PRSNT2 GND 31 73 GND PERxN13 73 32 GND RSVD 32 74 PETxP14 GND 74 33 PETxP4 RSVD 33 75 PETxN14 GND 75 34 PETxN4 GND 34 76 GND PERxP14 76 35 GND PERxP4 35 77 GND PERxN14 77 36 GND PERxN4 36 78 PETxP15 GND 78 37 PETxP5 GND 37 79...

Страница 75: ...PETp 3 27 GND 28 PETn 3 28 GND 29 GND 29 PERp 3 30 Reserved 30 PERn 3 31 PRSNT2 31 GND 32 GND 4X end 32 Reserved 33 33 Reserved 34 34 GND 35 GND 35 36 GND 36 37 37 GND 38 38 GND 39 GND 39 40 GND 40 41 41 GND 42 42 GND 43 GND 43 44 GND 44 45 45 GND 46 46 GND 47 GND 47 48 PRSNT2 48 49 GND 8X end 49 GND 7 4 2 VGA Connectors The following table details the pin out definition of the external VGA connec...

Страница 76: ...CCLK The following table details the pin out definition of the internal VGA connector J1D1 Table 40 VGA Internal Video Connector J1D1 Pin Signal Name Pin Signal Name 1 Red 2 R_RTN Red Return 3 Green 4 G_RTN Green Return 5 Blue 6 B_RTN Blue Return 7 Vsync 8 GND 9 Hsync GND 11 KEY 12 VIDEO_IN_USE signal 13 DDC_SDA 14 GND 15 DDC_SCL 16 5V 7 4 3 NIC Connectors The server board provides two stacked RJ ...

Страница 77: ...Intel Server Board S5500WB TPS Connector Header Locations and Pin out Revision 1 9 Intel order number E53971 008 63 Table 41 RJ 45 10 100 1000 NIC Connector Pin out J8A2 J9A1 ...

Страница 78: ... Ground 5 SATA_RX_N Negative side of receive differential pair 6 SATA_RX_P Positive side of receive differential pair 7 GND Ground 7 4 5 Intel I O Expansion Module Connector The server board provides 2x internal 50 pin Intel I O Expansion Module style connector J2B1 J3B1 to accommodate proprietary form factor Intel I O Expansion Modules which expand the I O capabilities of the server board without...

Страница 79: ...Intel Server Board S5500WB TPS Connector Header Locations and Pin out Revision 1 9 Intel order number E53971 008 65 Table 43 50 pin Intel I O Expansion Module Connector Pin out J2B1 J3B1 ...

Страница 80: ...he external USB connectors J7A1 J7A2 found on the back edge of the server board and the internal connector J9D3 centered on the right side of the board Table 46 External USB Connector J8A1 J9A1 Pin Signal Name Description 1 5V USB Power 2 USB_N Differential data line paired with DATAH0 3 USB_P Differential date line paired with DATAL0 4 GND Ground Two 2x5 connectors on the server board provide an ...

Страница 81: ... headers to be used for CPU and IO cooling The pin configuration for each of the 4 pin fan headers is identical and defined in the following tables Table 49 SSI 4 pin Fan Connector J2K2 J2K3 J3K1 J7K1 J8K4 J8K5 Pin Signal Name Description 1 GND Ground 2 12V Power Supply 12V 3 TACH IN FAN_TACH signal is connected to the BMC to monitor the fan speed 4 PWM OUT FAN_PWM signal to control fan speed Tabl...

Страница 82: ...erver management features of this server board require a 5 V stand by voltage is supplied from the power supply Some of the features and components that require this voltage must be present when the system is Off include the Integrated BMC onboard NICs and optional RMM3 connector with Intel RMM3 installed The LED is located in the lower left corner of the server board and is labeled 5VSB_LED is il...

Страница 83: ... LEDs Fan fault LEDs are present for the six fans and are located near each CPU fan header A FLTMEM2R E FLTCPU1 B FLTMEM2 F FLTCPU1A C FLTCPU2A G FLTMEM1 D FLTCPU2 H FLTMEM1R Figure 23 Fan Fault LED Locations 8 3 System Status LED The server board provides LED for system status The following figure shows the LED location ...

Страница 84: ...Intel Light Guided Diagnostics Intel Server Board S5500WB TPS Revision 1 9 Intel order number E53971 008 70 Figure 24 System Status LED Location The bi color System Status LED operates as follows ...

Страница 85: ... capabilities 2 CPU disabled if there are two CPUs and one CPU is disabled 3 Fan alarm Fan failure Number of operational fans should be more than minimum number needed to cool the system 4 Non critical threshold crossed Temperature voltage power nozzle power gauge and PROCHOT2 Therm Ctrl sensors 5 Battery failure 6 Predictive failure when the system has redundant power supplies Amber 1 Hz blink No...

Страница 86: ...smatch Integrated BMC Detected 1 CPU IERR signal asserted 2 CPU 1 is missing 3 CPU THERMTRIP 4 No power good power fault 5 Power Unit Redundancy sensor Insufficient resources offset indicates not enough power supplies are present Off N A Not ready AC power off Notes 1 The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide the contribution to the...

Страница 87: ... Guided Diagnostics Revision 1 9 Intel order number E53971 008 73 8 4 DIMM Fault LEDs Each DIMM slot has a DIMM Fault LED near the DIMM slot Figure 25 DIMM Fault LEDs Locations A FLT_F E FLT_A2 B FLT_E F FLT_A1 C FLT_D1 G FLT_B D FLT_D2 H FLT_C ...

Страница 88: ... number As each configuration routine is started the BIOS displays the given POST code to the POST code diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process you can use the Diagnostic LEDs to identify the last POST process executed For a complete description of how these LEDs are read and a list of all supported POST codes refer to...

Страница 89: ...cal temp voltage threshold battery failure or predictive PS failure Amber On Critical alarm Voltage thermal or power fault CPU1 missing insufficient power unit redundancy resource offset asserted Amber Blink Non Critical failure Critical temp voltage threshold VDR hot asserted min number fans not present or failed Off AC power off System unplugged AC power on System powered off and in standby no p...

Страница 90: ...sors Discrete board level digital thermal sensor TMP75 Front panel Temp Sensor if present CPU PECI DTS DDR3 RDIMM TSOD Eight front system fan headers for four individual thermal zones Zone 4 mem2 fans responds to memory2 and CPU2 temperatures Zone 3 CPU2 and MEM2 fans responds to CPU2 and IOH temperatures Zone 2 CPU1 and MEM1 fans responds to CPU1 and IOH temperatures Zone 1 mem1 fans responds to ...

Страница 91: ...e second is the PWM signal name the third is the Tach and the forth is the reference description The last is the signal name associated with the fault LED signal Figure 28 Location of Fan Connectors Table 53 Fan Connector Location Detail CPU 1 Memory 1 FAN_CPU1 FAN_CPU1A FAN_MEM1 FAN_MEM1R PWM_CPU1 PWM_CPU1 PWM_MEM1 PWM_MEM1 Tach 1 Tach 5 Tach 2 Tach 2 6 J8E1 J8J4 J8J3 J9E1 LED_Fan_Fault_CPU1 LED_...

Страница 92: ...9 Fans and Sensors Block Diagram 9 2 Thermal Sensors 9 2 1 Processor PECI Temperature Sensor The processor thermal control uses a CPU PECI thermal sensor which is a relative temperature off PROCHOT trip point a 20C reading means 20C below PROCHOT trip point temperature The BMC can get the processor PECI Tcontrol values for each CPU installed to use follow the clamped algorithm for component therma...

Страница 93: ...e configured by BIOS MRC and remain fixed after post Static closed loop thermal throttling The system does not change the control registers for a closed loop in the processor during runtime CLTT control registers are configured by BIOS MRC For advanced implementation with dynamic OLTT and CLTT refer to the VR_Hot Sensor in VR11 1 9 2 3 Board Temperature Sensor For rack based systems or those syste...

Страница 94: ...tel order number E53971 008 80 Figure 30 Temp Sensor Location Location Description A U4K3 Temp Sensor TMP75 9 3 Heatsinks The Intel Server Board S5500WB system cooling solutions rely on heatsinks for CPU cooling Chipset and or voltage regulator heatsinks are compatible with the 1U usage ...

Страница 95: ...Independent Loading Mechanism ILM and Unified Backplate at each processor socket The URS retention transfers load to the server board via the unified backplate assembly The URS spring captive in the heatsink provides the necessary compressive load for the thermal interface material All components of the URS heatsink solution are captive to the heatsink and only require a Philips screwdriver to att...

Страница 96: ...oller which is capable of throttling the CPU via PROCHOT Some simple masking circuitry is required to prevent the VRHOT from asserting the PROCHOT to the CPUs at the time of CPU_RST This keeps the VRHOT from unintentionally causing the CPU to disable FW monitors VRHOT and creates a SEL event if VRHOT is asserted There is no fan action as a result of the BMC seeing VRHOT 9 4 2 THERMTRIP THERMTRIP c...

Страница 97: ...lti rail power supply that adheres to the SSI power specification Power Supply Design Guideline for 2008 Dual Socket Servers and Workstations You can view SSI specifications at the following website http ssiforum org 12V SKU This version of the server board is designed to work with specially designed single rail power supplies that provide 12V and 5V standby current The server board has integrated...

Страница 98: ... a DC 12 V only power supply is recommended Appendix A shows connector pin outs PMbus communications between the power supply and server board must comply with both SMBus and I2C Bus timing requirements 10 3 Power Sequencing and Reset Distribution The IBMC device is integrated into the power control and reset logic of the system This design reduces the discrete logic requirements of previous gener...

Страница 99: ...rope IEC60950 International CB Certificate Report IEC60950 report to include all country national deviations GOST R 50377 92 Listed on one System Certification Russia Belarus Certification Listed on System Certification Belarus CE Low Voltage Directive 73 23 EEE Europe IRAM Certification Argentina 11 1 2 Product EMC Compliance Class A Compliance FCC ICES 003 Emissions USA Canada Verification CISPR...

Страница 100: ...able 55 Product Regulatory Compliance Markings 11 3 Electromagnetic Compatibility Notices 11 3 1 FCC Verification Statement USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation Regul...

Страница 101: ...nto an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product Only peripherals computer input outpu...

Страница 102: ...1 3 4 BSMI Taiwan The BSMI Certification Marking and EMC warning is located on the outside rear area of the product 11 3 5 KCC Korea Following is the KCC certification information for Korea English translation of the notice above 1 Type of Equipment Model Name On Certification and Product 2 Certification No On KCC certificate Obtain certificate from local Intel representative 3 Name of Certificati...

Страница 103: ...ng the POST process the diagnostic LEDs can be used to identify the last POST process to be executed Each POST code is represented by the eight amber diagnostic LEDs The POST codes are divided into two nibbles an upper nibble and a lower nibble The upper nibble bits are represented by diagnostic LEDs 4 5 6 and 7 The lower nibble bits are represented by diagnostics LEDs 0 1 2 and 3 If the bit is se...

Страница 104: ...the diagnostic LED decoder The LEDs are decoded as follows Table 56 POST Progress Code LED Example LEDs Upper Nibble LEDs Lower Nibble LEDs MSB LSB LED 7 LED 6 LED 5 LED 4 LED 3 LED 2 LED 1 LED 0 8h 4h 2h 1h 8h 4h 2h 1h Status ON OFF ON OFF ON ON OFF OFF Results 1 0 1 0 1 1 0 0 Ah Ch Upper nibble bits 1010b Ah Lower nibble bits 1100b Ch the two are concatenated as ACh ...

Страница 105: ...nfiguration data from memory SPD on FBDIMM 0x23h 0 0 1 0 0 0 1 1 Detecting presence of memory 0x24h 0 0 1 0 0 1 0 0 Programming timing parameters in the memory controller 0x25h 0 0 1 0 0 1 0 1 Configuring memory parameters in the memory controller 0x26h 0 0 1 0 0 1 1 0 Optimizing memory controller settings 0x27h 0 0 1 0 0 1 1 1 Initializing memory such as ECC init 0x28h 0 0 1 0 1 0 0 0 Testing mem...

Страница 106: ... 0 1 1 Memory Initialization of Integrated Memory Controller 0xB4h 1 0 1 1 0 1 0 0 Memory Initialization of Integrated Memory Controller 0xB5h 1 0 1 1 0 1 0 1 Memory Initialization of Integrated Memory Controller 0xB6h 1 0 1 1 0 1 1 0 Memory Initialization of Integrated Memory Controller 0xB7h 1 0 1 1 0 1 1 1 Memory Initialization of Integrated Memory Controller 0xB8h 1 0 1 1 1 0 0 0 Memory Initia...

Страница 107: ... 1 1 1 0 0 1 1 Reserved for video controller VGA Remote Console 0x78h 0 1 1 1 1 0 0 0 Resetting the console controller 0x79h 0 1 1 1 1 0 0 1 Disabling the console controller 0x7Ah 0 1 1 1 1 0 1 0 Enabling the console controller 0x7Bh 0 1 1 1 1 0 1 1 Reserved for console controller Keyboard only USB 0x90h 1 0 0 1 0 0 0 0 Resetting the keyboard 0x91h 1 0 0 1 0 0 0 1 Disabling the keyboard 0x92h 1 0 ...

Страница 108: ...ansfer control to EFI boot 0xD6 1 1 0 1 0 1 1 0 Trying to boot device selection 0xDF 1 1 0 1 1 1 1 1 Reserved for boot device selection Pre EFI Initialization PEI Core 0xE0h 1 1 1 0 0 0 0 0 Entered Pre EFI Initialization phase PEI 0xE1h 1 1 1 0 0 0 0 1 Started dispatching early initialization modules PEIM 0xE2h 1 1 1 0 0 0 1 0 Initial memory found configured and installed correctly 0xE3h 1 1 1 0 0...

Страница 109: ...of a user request 0x31h 0 0 1 1 0 0 0 1 Crisis recovery initiated by software corrupt flash 0x34h 0 0 1 1 0 1 0 0 Loading crisis recovery capsule 0x35h 0 0 1 1 0 1 0 1 Handing off control to the crisis recovery capsule 0x36h 0 0 1 1 0 1 1 0 Begin crisis recovery 0x3Eh 0 0 1 1 1 1 1 0 No crisis recovery capsule detected 0x3Fh 0 0 1 1 1 1 1 1 Crisis recovery capsule failed integrity check of capsule...

Страница 110: ...g determines whether the system pauses to the Error Manager for this type of error where the user can take immediate corrective action or choose to continue booting Halt The message is displayed on the Error Manager screen an error is logged to the SEL and the system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system The setup POST error Pause...

Страница 111: ...6 DIMM_D1 failed Self Test BIST Major 8527 DIMM_D2 failed Self Test BIST Major 8528 DIMM_E1 failed Self Test BIST Major 8529 DIMM_E2 failed Self Test BIST Major 852A DIMM_F1 failed Self Test BIST Major 852B DIMM_F2 failed Self Test BIST Major 8540 DIMM_A1 Disabled Major 8541 DIMM_A2 Disabled Major 8542 DIMM_B1 Disabled Major 8543 DIMM_B2 Disabled Major 8544 DIMM_C1 Disabled Major 8545 DIMM_C2 Disa...

Страница 112: ...oller error Minor 9243 Mouse component was not detected Minor 9246 Mouse component encountered a controller error Minor 9266 Local Console component encountered a controller error Minor 9268 Local Console component encountered an output error Minor 9269 Local Console component encountered a resource conflict error Minor 9286 Remote Console component encountered a controller error Minor 9287 Remote...

Страница 113: ...ountered a mismatch error Major 0xA027 Processor component encountered a low voltage error Minor 0xA028 Processor component encountered a high voltage error Minor 0xA421 PCI component encountered a SERR error Fatal 0xA500 ATA ATPI ATA bus SMART not supported Minor 0xA501 ATA ATPI ATA SMART is disabled Minor 0xA5A0 PCI Express component encountered a PERR error Minor 0xA5A1 PCI Express component en...

Страница 114: ...CATERR On a catastrophic hardware event the core signals CATERR to the uncore The core enters a halted state that can only be exited by a reset CBC Chassis Bridge Controller A microcontroller connected to one or more other CBCs together they bridge the IPMB buses of multiple chassis CEK Common Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS In terms of this specification this de...

Страница 115: ...ork LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024KB ME Management Engine MD2 Message Digest 2 Hashing Algorithm MD5 Message Digest 5 Hashing Algorithm Higher Security ms Milliseconds MTTR Memory Type Range Register Mux Multiplexor NIC Network Interface Controller NMI Nonmaskable Interrupt OBF Output Buffer OEM Origina...

Страница 116: ...grammable Read Only Memory SEL System Event Log SIO Server Input Output SMBUS System Management BUS SMI Server Management Interrupt SMI is the highest priority nonmaskable interrupt SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TDP Thermal Design Power TIM Thermal Interface Material UART Universal Asynchronous Receiver Transm...

Страница 117: ...ger 1 5 External Interface Specification using IPMI 2007 Intel Corporation Node Power and Thermal Management Architecture Specification v1 5 rev 0 79 2007 Intel Corporation Intel Server System Integrated Baseboard Management Controller Core External Product Specification 2007 Intel Corporation Intel Thurley Server Platform Services IPMI Commands Specification 2007 Intel Corporation Intelligent Pla...

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