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Quad-Core Intel® Xeon® Processor 5300 Series Datasheet

Signal Definitions

5.1

Signal Definitions

Table 5-1.

Signal Definitions (Sheet 1 of 7)

Name

Type

Description

Notes

A[37:3]#

I/O

A[37:3]# (Address) define a 2

-byte physical memory address space. In sub-phase

1 of the address phase, these signals transmit the address of a transaction. In sub-

phase 2, these signals transmit transaction type information. These signals must

connect the appropriate pins of all agents on the FSB. A[37:3]#

are protected by

parity signals AP[1:0]#. A[37:3]#

are source synchronous signals and are latched

into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a subset of the

A[37:3]#

lands to determine their power-on configuration. See

Section 7.1

3,4

A20M#

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20

(A20#) before looking up a line in any internal cache and before driving a read/write

transaction on the bus. Asserting A20M# emulates the 8086 processor's address

wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real

mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address

on the A[37:3]#

lands. All bus agents observe the ADS# activation to begin parity

checking, protocol checking, address decode, internal snoop, or deferred reply ID

match operations associated with the new transaction. This signal must be connected

to the appropriate pins on all Quad-Core Intel® Xeon® Processor 5300 Series FSB

agents.

ADSTB[1:0]#

I/O

Address strobes are used to latch A[37:3]#

and REQ[4:0]# on their rising and falling

edge. Strobes are associated with signals as shown below.

3,4

AP[1:0]#

I/O

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,

A[37:3]#

, and the transaction type on the REQ[4:0]# signals. A correct parity signal

is high if an even number of covered signals are low and low if an odd number of

covered signals are low. This allows parity to be high when all the covered signals are

high. AP[1:0]# must be connected to the appropriate pins of all Quad-Core Intel®

Xeon® Processor 5300 Series FSB agents. The following table defines the coverage

model of these signals.

3,4

BCLK[1:0]

The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency.

All processor FSB agents must receive these signals to drive their outputs and latch

their inputs.
All external timing parameters are specified with respect to the rising edge of BCLK0

crossing V

CROSS

Signals

Associated Strobes

REQ[4:0], A[16:3]#,

A[37:36]#

ADSTB0#

A[35:17]#

ADSTB1#

Request Signals

Subphase 1

Subphase 2

A[37:24]#

AP0#

AP1#

A[23:3]#

AP1#

AP0#

REQ[4:0]#

AP1#

AP0#

Содержание Quad-Core Xeon

Страница 1: ...Order Number 315569 003 Quad Core Intel Xeon Processor 5300 Series Datasheet September 2007...

Страница 2: ...uture changes to them The Quad Core Intel Xeon Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current c...

Страница 3: ...aracteristics 26 2 10 2 Input Device Hysteresis 27 2 11 Mixing Processors 27 2 12 Absolute Maximum and Minimum Ratings 28 2 13 Processor DC Specifications 29 2 13 1 Flexible Motherboard Guidelines FMB...

Страница 4: ...ink Support CEK 121 8 3 Electrical Requirements 121 8 3 1 Fan Power Supply Active CEK 121 8 3 2 Boxed Processor Cooling Requirements 122 8 4 Boxed Processor Contents 123 9 Debug Tools Specifications 1...

Страница 5: ...rement Location 98 6 7 Thermal Monitor 2 Frequency and Voltage Ordering 100 6 8 PECI Topology 102 6 9 Conceptual Fan Control Diagram For A PECI Based Platform 103 7 1 Stop Clock State Machine 108 8 1...

Страница 6: ...ignal Definitions 79 6 1 Quad Core Intel Xeon Processor E5300 Series Thermal Specifications 89 6 2 Quad Core Intel Xeon Processor E5300 Series Thermal Profile Table 90 6 3 Quad Core Intel Xeon Process...

Страница 7: ...sheet 7 Revision History Revision Description Date 001 Initial Release November 2006 002 Added Quad Core Intel Xeon Processor L5300 Series March 2007 003 Included the G step information Added the Quad...

Страница 8: ...8 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 9: ...in high temperature situations Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations The Quad Core Intel Xeon Processor 5300 Series features include A...

Страница 10: ...ill support the power requirements of all frequencies of the processors including Flexible Motherboard Guidelines FMB see Section 2 13 1 Refer to the appropriate platform design guidelines for impleme...

Страница 11: ...Xeon Processor E5300 Series SKU Quad Core Intel Xeon Processor X5300 Series An accelerated performance version of the Quad Core Intel Xeon Processor 5300 Series For this document Quad Core Intel Xeon...

Страница 12: ...connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handl...

Страница 13: ...ermination voltage Note In some Intel processor EMTS documents VTT is instead called VCCP 1 2 State of Data The data contained within this document is the most accurate information available by the pu...

Страница 14: ...ntel representative for the latest revision of these documents Quad Core Intel Xeon Processor 5300 Series Thermal Mechanical Design Guidelines Clovertown Processor Boundary Scan Descriptive Language B...

Страница 15: ...EF_DATA_MID GTLREF_DATA_END GTLREF_ADD_MID and GTLREF_ADD_END which are used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF_DATA_MID and GTLREF_DATA_END are used for th...

Страница 16: ...m a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 12 Failure to do so can result...

Страница 17: ...mum speed of the processor It is possible to override this setting using software see the Conroe and Woodcrest Processor Family BIOS Writer s Guide This permits operation at lower frequencies than the...

Страница 18: ...ions Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All FSB...

Страница 19: ...ded in Table 2 3 is not related in any way to previous Intel Xeon processors or voltage regulator designs If the processor socket is empty VID 6 1 111111 or the voltage regulation circuit cannot suppl...

Страница 20: ...5 mV VCC_MAX 7A 1 1 1 1 0 1 0 8500 3C 0 1 1 1 1 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 1 1 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0...

Страница 21: ...tform design guidelines For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors RTT For details see Table 2 20 Some TAP CMOS inputs and outputs...

Страница 22: ...their respective strobe lines data and address as well as rising edge of BCLK0 Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 6...

Страница 23: ..._MID GTLREF_DATA_END LL_ID 1 0 MS_ID 1 0 PECI RESERVED SKTOCC TESTHI 11 10 TESTHI 7 0 TESTIN1 TESTIN2 VCC VCC_DIE_SENSE VCC_DIE_SENSE2 VCCPLL VID_SELECT VSS_DIE_SENSE VSS_DIE_SENSE2 VSS VTT VTT_OUT VT...

Страница 24: ...and TRST Two copies of each signal may be required with each driving a different voltage level 2 10 Platform Environmental Control Interface PECI DC Specifications PECI is an Intel proprietary one wir...

Страница 25: ...core frequency number of cores and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Combining...

Страница 26: ...g absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned t...

Страница 27: ...elines FMB The Flexible Motherboard FMB guidelines are estimates of the maximum values the Quad Core Intel Xeon Processor 5300 Series will have over certain time periods The values are only estimates...

Страница 28: ...h FMB 60 A 4 5 6 9 ICC_RESET ICC_RESET for Quad Core Intel Xeon Processor L5300 Series processor core with multiple VID Launch FMB 60 A 17 ICC ICC for Quad Core Intel Xeon Processor L5318 core with mu...

Страница 29: ...D transitions below the specified VID 11 Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings 12 This spec...

Страница 30: ...tion Notes 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC 2 Not 100 tested Specified by design characterization Notes 1 Processor...

Страница 31: ...es 1 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC Figure 2 4 Quad Core Intel Xeon Processor X5365 Series Load Current versus Time...

Страница 32: ...s Sheet 1 of 2 ICC A VCC_Max V VCC_Typ V VCC_Min V Notes 0 VID 0 000 VID 0 015 VID 0 030 1 2 3 5 VID 0 006 VID 0 021 VID 0 036 1 2 3 10 VID 0 013 VID 0 028 VID 0 043 1 2 3 15 VID 0 019 VID 0 034 VID 0...

Страница 33: ...ecify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands Voltage regulation feedback for voltage regulator circuits...

Страница 34: ...cessor VID information 3 Refer to Table 2 13 for VCCStatic and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC_DIE_SENSE and VSS_DIE_SENSE lands and the VCC_...

Страница 35: ...r socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Figure 2 9 Quad Core Intel Xeon Processor L5300 Series VCC St...

Страница 36: ...to the appropriate platform design guide for details on VR implementation 50 VID 0 063 VID 0 073 VID 0 083 1 2 3 55 VID 0 069 VID 0 079 VID 0 089 1 2 3 60 VID 0 075 VID 0 085 VID 0 095 1 2 3 65 VID 0...

Страница 37: ...ck for voltage regulator circuits must also be taken from processor VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands Refer to the Voltage Regulator Module VRM and Ente...

Страница 38: ...r VCC_DIE_SENSE and VSS_DIE_SENSE lands and VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for sock...

Страница 39: ...guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Notes 1 Unless otherwise noted all specifications in this table apply to all pr...

Страница 40: ...short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID VOS_MAX VOS_MAX is the maximum allowabl...

Страница 41: ...ntegrated into the processor silicon See Table 2 7 for details on which signals do not include on die termination Please refer to Table 2 20 for RTT values Valid high and low levels are determined by...

Страница 42: ...mV and 455 mV of the clock swing 3 Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of BCLK1 4 VHavg is the statistical averag...

Страница 43: ...des input threshold hysteresis 9 The crossing point must meet the absolute and relative crossing point specifications simultaneously 10 VHavg can be measured directly using Vtop on Agilent and High on...

Страница 44: ...ion Crossing Voltage Threshold Region VH VL Overshoot Undershoot Ringback Margin Rising Edge Ringback Falling Edge Ringback BCLK0 BCLK1 Crossing Voltage Tp Tp T1 BCLK 1 0 period 660 670 680 690 700 71...

Страница 45: ...1 socket The package components shown in Figure 3 1 include the following Integrated Heat Spreader IHS Thermal Interface Material TIM Processor Die Package Substrate Landside capacitors Package Lands...

Страница 46: ...00 Series Datasheet Note Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Desig...

Страница 47: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 49 Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 3...

Страница 48: ...Mechanical Specifications 50 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 3 4 Processor Package Drawing Sheet 3 of 3...

Страница 49: ...3 These specifications are based on limited testing for design characterization Loading limits are for the LGA771 socket 4 Dynamic compressive load applies to all board thickness 5 Dynamic loading is...

Страница 50: ...ling guidelines are for the package only and do not include the limits of the processor socket 3 5 Package Insertion Specifications The Quad Core Intel Xeon Processor 5300 Series can be inserted and r...

Страница 51: ...he top and bottom view of the processor land coordinates respectively The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Processor Top side Markings Example...

Страница 52: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM...

Страница 53: ...2 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH A...

Страница 54: ...Mechanical Specifications 56 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 55: ...t A12 U5 Source Sync Input Output A13 U4 Source Sync Input Output A14 V5 Source Sync Input Output A15 V4 Source Sync Input Output A16 W5 Source Sync Input Output A17 AB6 Source Sync Input Output A18 W...

Страница 56: ...Input COMP3 R1 Power Other Input D00 B4 Source Sync Input Output Table 4 1 Land Listing by Land Name Sheet 3 of 23 Pin Name Pin No Signal Buffer Type Direction D01 C5 Source Sync Input Output D02 A4 S...

Страница 57: ...put Output D52 C14 Source Sync Input Output Table 4 1 Land Listing by Land Name Sheet 5 of 23 Pin Name Pin No Signal Buffer Type Direction D53 B15 Source Sync Input Output D54 C18 Source Sync Input Ou...

Страница 58: ...ut MCERR AB3 Common Clk Input Output MS_ID0 W1 Power Other Output MS_ID1 V1 Power Other Output PECI G5 Power Other Input Output PROCHOT AL2 Open Drain Asynchronous Output PWRGOOD N1 CMOS Asynchronous...

Страница 59: ...her VCC AB8 Power Other VCC AC23 Power Other VCC AC24 Power Other VCC AC25 Power Other Table 4 1 Land Listing by Land Name Sheet 9 of 23 Pin Name Pin No Signal Buffer Type Direction VCC AC26 Power Oth...

Страница 60: ...AJ9 Power Other VCC AK11 Power Other Table 4 1 Land Listing by Land Name Sheet 11 of 23 Pin Name Pin No Signal Buffer Type Direction VCC AK12 Power Other VCC AK14 Power Other VCC AK15 Power Other VCC...

Страница 61: ...Other VCC K30 Power Other VCC K8 Power Other Table 4 1 Land Listing by Land Name Sheet 13 of 23 Pin Name Pin No Signal Buffer Type Direction VCC L8 Power Other VCC M23 Power Other VCC M24 Power Other...

Страница 62: ...24 Power Other VSS AA25 Power Other VSS AA26 Power Other VSS AA27 Power Other Table 4 1 Land Listing by Land Name Sheet 15 of 23 Pin Name Pin No Signal Buffer Type Direction VSS AA28 Power Other VSS A...

Страница 63: ...S AJ28 Power Other VSS AJ29 Power Other Table 4 1 Land Listing by Land Name Sheet 17 of 23 Pin Name Pin No Signal Buffer Type Direction VSS AJ30 Power Other VSS AJ4 Power Other VSS AK10 Power Other VS...

Страница 64: ...her VSS E26 Power Other VSS E27 Power Other Table 4 1 Land Listing by Land Name Sheet 19 of 23 Pin Name Pin No Signal Buffer Type Direction VSS E28 Power Other VSS E8 Power Other VSS F1 Power Other VS...

Страница 65: ...ower Other Table 4 1 Land Listing by Land Name Sheet 21 of 23 Pin Name Pin No Signal Buffer Type Direction VSS V24 Power Other VSS V25 Power Other VSS V26 Power Other VSS V27 Power Other VSS V28 Power...

Страница 66: ...68 Quad Core Intel Xeon Processor 5300 Series Datasheet VTT_OUT J1 Power Other Output VTT_SEL F27 Power Other Output Table 4 1 Land Listing by Land Name Sheet 23 of 23 Pin Name Pin No Signal Buffer Ty...

Страница 67: ...ower Other AA27 VSS Power Other AA28 VSS Power Other AA29 VSS Power Other AA3 VSS Power Other AA30 VSS Power Other AA4 A21 Source Sync Input Output AA5 A23 Source Sync Input Output AA6 VSS Power Other...

Страница 68: ...SERVED AE7 VSS Power Other Table 4 2 Land Listing by Land Number Sheet 3 of 20 Pin No Pin Name Signal Buffer Type Direction AE8 SKTOCC Power Other Output AE9 VCC Power Other AF1 TDO TAP Output AF10 VS...

Страница 69: ...AH24 VSS Power Other AH25 VCC Power Other Table 4 2 Land Listing by Land Number Sheet 5 of 20 Pin No Pin Name Signal Buffer Type Direction AH26 VCC Power Other AH27 VCC Power Other AH28 VCC Power Oth...

Страница 70: ...Other Table 4 2 Land Listing by Land Number Sheet 7 of 20 Pin No Pin Name Signal Buffer Type Direction AL17 VSS Power Other AL18 VCC Power Other AL19 VCC Power Other AL2 PROCHOT Open Drain Asynchrono...

Страница 71: ...f 20 Pin No Pin Name Signal Buffer Type Direction B11 VSS Power Other B12 D13 Source Sync Input Output B13 RESERVED B14 VSS Power Other B15 D53 Source Sync Input Output B16 D55 Source Sync Input Outpu...

Страница 72: ...Power Other D28 VTT Power Other D29 VTT Power Other Table 4 2 Land Listing by Land Number Sheet 11 of 20 Pin No Pin Name Signal Buffer Type Direction D3 VSS Power Other D30 VTT Power Other D4 HIT Comm...

Страница 73: ...Output G18 D35 Source Sync Input Output G19 DSTBP2 Source Sync Input Output G2 COMP2 Power Other Input Table 4 2 Land Listing by Land Number Sheet 13 of 20 Pin No Pin Name Signal Buffer Type Direction...

Страница 74: ...J9 VCC Power Other Table 4 2 Land Listing by Land Number Sheet 15 of 20 Pin No Pin Name Signal Buffer Type Direction K1 LINT0 CMOS Asynchronous Input K2 VSS Power Other K23 VCC Power Other K24 VCC Pow...

Страница 75: ...S Power Other Table 4 2 Land Listing by Land Number Sheet 17 of 20 Pin No Pin Name Signal Buffer Type Direction P5 A37 Source Sync Input Output P6 A04 Source Sync Input Output P7 VSS Power Other P8 VC...

Страница 76: ...Power Other W1 MS_ID0 Power Other Output W2 TESTIN1 Power Other Input W23 VCC Power Other W24 VCC Power Other W25 VCC Power Other W26 VCC Power Other Table 4 2 Land Listing by Land Number Sheet 19 of...

Страница 77: ...ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 37 3 4 lands All bus agents observe the ADS activation to begin parity checking protocol checking address d...

Страница 78: ...tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be b...

Страница 79: ...the system board DBR is used by a debug port interposer so that an in target probe can drive reset If a debug port connector is implemented in the system DBR is a no connect on the Quad Core Intel Xeo...

Страница 80: ...Circuit TCC GTLREF_ADD_MID GTLREF_ADD_END I GTLREF_ADD determines the signal reference level for AGTL address and common clock input lands GTLREF_ADD is used by the AGTL receivers to determine if a si...

Страница 81: ...s to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the begin...

Страница 82: ...and must connect the appropriate pins of all processor FSB agents 3 RSP I RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during ass...

Страница 83: ...st connect the appropriate pins of all FSB agents TRST I TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VCCPLL I The Quad Core Intel Xeon Processor...

Страница 84: ...Signal Definitions 86 Quad Core Intel Xeon Processor 5300 Series Datasheet...

Страница 85: ...ications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TCASE specifications as def...

Страница 86: ...y TCASE_MAX P_PROFILE_MIN P_PROFILE_MIN is defined as the processor power at which TCASE calculated from the thermal profile is equal to 50 C Analysis indicates that real applications are unlikely to...

Страница 87: ...ns Thermal Mechanical Design Guidelines for details on system thermal solution design thermal profiles and environmental considerations Notes 1 These values are specified at VCC_MAX for all processor...

Страница 88: ...l implementation details Figure 6 1 Quad Core Intel Xeon Processor E5300 Series Thermal Profile 40 45 50 55 60 65 70 0 10 20 30 40 50 60 70 80 Power W Tcase C Thermal Profile Y 0 293 x 42 6 40 45 50 5...

Страница 89: ...s Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 3 for details on TCC activation 3 Quad Core Intel Xeon Processor X530...

Страница 90: ...5 50 2 50 51 1 55 51 9 60 52 8 65 53 6 70 54 5 75 55 3 80 56 2 85 57 0 90 57 9 95 58 7 100 59 6 105 60 5 110 61 3 115 62 2 120 63 0 Table 6 5 Quad Core Intel Xeon Processor X5300 Series Thermal Profil...

Страница 91: ...ization 5 Power specifications are defined at all VIDs found in Table 2 3 The Quad Core Intel Xeon Processor L5300 Series may be shipped under multiple VIDs for each frequency 6 FMB or Flexible Mother...

Страница 92: ...ASE 4 These specifications are based on silicon characterization 5 Power specifications are defined at all VIDs found in Table 2 3 The Quad Core Intel Xeon Processor L5300 Series may be shipped under...

Страница 93: ...exceeds VCC_MAX at specified ICC Please refer to the loadline specifications in Section 2 2 Maximum Power is the highest power the processor will dissipate regardless of its VID Maximum Power is meas...

Страница 94: ...that constitute the thermal profile 2 Refer to the Quad Core Intel Xeon Processor L5318 Thermal Mechanical Design Guidelines for system and environmental implementation details 3 The Nominal Thermal...

Страница 95: ...logy The minimum and maximum case temperatures TCASE are specified in Table 6 1 through Table 6 7 and are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 6...

Страница 96: ...d Thermal Monitor TM2 The TM1 and TM2 must both be enabled in BIOS for the processor to be operating within specifications When both are enabled TM2 will be activated first and TM1 will be added if TM...

Страница 97: ...e processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Quad Core Intel Xeon P...

Страница 98: ...the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to insure proper operation once the processor reaches its...

Страница 99: ...ip temperature or the case temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of TCASE or PROCHOT 6 3 6 FORCEPR Si...

Страница 100: ...een the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2 Kbps to 2 Mbps The PECI interface on Quad Core Intel Xeon Processor 5300 Series...

Страница 101: ...times to determine the appropriate sample rate based on the controller s fan control algorithm and targeted response rate The key items to take into account when settling on a fan control algorithm a...

Страница 102: ...to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI...

Страница 103: ...ow Power States Quad Core Intel Xeon Processor 5300 Series support the Extended HALT state also referred to as C1E in addition to the HALT state and Stop Grant state to reduce power consumption by sto...

Страница 104: ...ftware Developer s Manual Volume III System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the proces...

Страница 105: ...e 34W 3 G 0 stepping SKUs with Extended HALT state are specified at TCASE 40 C Table 7 2 Extended HALT Maximum Power B 3 Stepping G 0 Stepping Symbol FSB Speed MHz TCASE C Max W TCASE C Max W Notes PE...

Страница 106: ...s state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched an...

Страница 107: ...e in Stop Grant state or in HALT state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side b...

Страница 108: ...the four processor cores is selected for that processor package Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption th...

Страница 109: ...primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and strong side directional airflow is not an issue The 1U passive 3U active combination solution with t...

Страница 110: ...ed that the CEK spring will ship with the base board and be pre attached prior to shipping Figure 8 2 Boxed Quad Core Intel Xeon Processor 5300 Series 2U Passive Heat Sink Figure 8 3 2U Passive Quad C...

Страница 111: ...rocessor will be shipped with an unattached thermal solution Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling The physical space requirements and dimens...

Страница 112: ...Boxed Processor Specifications 114 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 4 Top Side Board Keepout Zones Part 1...

Страница 113: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 115 Boxed Processor Specifications Figure 8 5 Top Side Board Keepout Zones Part 2...

Страница 114: ...Boxed Processor Specifications 116 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 6 Bottom Side Board Keepout Zones...

Страница 115: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 117 Boxed Processor Specifications Figure 8 7 Board Mounting Hole Keepout Zones...

Страница 116: ...Boxed Processor Specifications 118 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 8 Volumetric Height Keep Ins...

Страница 117: ...Quad Core Intel Xeon Processor 5300 Series Datasheet 119 Boxed Processor Specifications Figure 8 9 4 Pin Fan Cable Connector For Active CEK Heat Sink...

Страница 118: ...Boxed Processor Specifications 120 Quad Core Intel Xeon Processor 5300 Series Datasheet Figure 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink...

Страница 119: ...such that the dynamic loads from the heat sink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures...

Страница 120: ...sign considerations Meeting the processor s temperature specifications is also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The pr...

Страница 121: ...sink fan Use of the active configuration in a 2U rackmount chassis is not recommended It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing...

Страница 122: ...or 5300 Series Datasheet The other items listed in Figure 8 3 that are required to compete this solution will be shipped with either the chassis or boards They are as follows CEK Spring supplied by ba...

Страница 123: ...multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Quad Core Intel Xeon Processor 5300 Series based systems designs including...

Страница 124: ...ytic capacitors fall inside of the keepout volume for the LAI In this case it is necessary to move these capacitors to the backside of the board before using the LAI Additionally note that it is possi...

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