Evaluation Platform Board Manual
41
Intel
®
IQ80332 I/O Processor
Hardware Reference Section
3.9.6.4.3
S7A1-3: Configration Cycle Enable corresponding to signal name PBI_AD6
Configuration Cycle Enable or RETRY is latched at the de-asserting edge of P_RST# and it
determines when the Primary PCI interface disable PCI configuration cycles by signaling a Retry
until the Configuration Cycle Retry bit is cleared in the PCI Configuration and Status Register.
3.9.6.4.4
S7A1-4: PCI-X Bus B Speed Enable corresponding to signal name PBI_AD10
This switch allows the user to enables 133 MHz on PCI-X segment B.
Table 24.
S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode
3.9.6.4.5
S7A1-5: PCI-X Bus B Hot-Plug Reset Disable corresponding to signal name
PBI_AD11
This switch allows the user to enables or disable Hot-Plug Reset on PCI-X segment B.
Table 25.
S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode
3.9.6.4.6
Switch S7A1- 6: Hot Plug Capable Disabled corresponding to signal name
PBI_AD15
This switch allows the user to enable hot plug devices on the secondary PCI-X bus B.
Table 26.
Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode
Table 23.
Switch S7A1-3: RETRY: Settings and Operation Mode
S7A1-3
Operation Mode
Open
Configuration Retry Enabled. - use when booting in a host (Default mode).
Closed
Configuration Retry Disabled.
S7A1-4
Operation Mode
Open
Enables 133 MHz on PCI-X bus B.
Closed
Enables 100 MHz on PCI-X bus B (Default Mode).
S7A1-5
Operation Mode
Open
PCI-X Bus B Hot-Plug Enable, normal reset mode disabled
Closed
PCI-X Bus B Hot-Plug Disable, normal reset mode (Default Mode).
S7A1-6
Operation Mode
Open
Hot Plug on Bus B Enabled
Closed
Disables Hot Plug on Bus B(Default mode)
