Intel PC50HP, Руководство по обслуживанию

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Sheet 35 of 79
eDP 2-to-1 PS8461
SW
Schematic Diagrams
B - 36 eDP 2-to-1 PS8461 SW
B.Schematic Diagrams
eDP 2-to-1 PS8461 SW
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To eDP Panel CONN
DIFF=100ohm
CFG0 Operation mode configuration for Input port#1:
L:DP Port is configured to Auto jitter cleaning mode
(default)
M:DP Port is configured to Redriving mode
H:DP Port is configured to Full jitter cleaning mode
SW=
L: Port1 is selected as the input port
H: Port2 is selected as the input port
I2C_ADDR =
L:Default I2C address, 0x10-0x2F
H:Alternative I2C address, 0x90-0x9F and
0xD0-0xDF
CFG4 Operation mode configuration for Input port#2:
L:DP Port is configured to Auto jitter cleaning mode
(default)
M:DP Port is configured to Redriving mode
H:DP Port is configured to Full jitter cleaning mode
Auto EQ option for Input Port1
CFG1 =
L:Auto EQ enabled (default)
EQ automatically adjusted based on link training.
H:Auto EQ disabled.
Auto EQ option for Input Port2
CFG3 =
L:Auto EQ enabled (default)
EQ automatically adjusted based on link training.
H:Auto EQ disabled.
CFG2 Output Configuration ϗ
L: DP output is dynamic adjusted based on link training (default)
M: DP output is fixed to 400mV/0dB
H: DP output is fixed to 800mV/3.5dB
VDD_DDC: DDC Passive Switch Supply Power.
It should be connected with 1.8V or 3.3V
which depends on the DDC IO voltage of source IC
FROM PCH (GPP_F9)
HIGH=PS8331B PORT2 (dGPU)
LOW=PS8331B PORT1 (iGPU) (DEFAULT)
FROM DDS FUNCTION
From Nvidia
Frome Intel
CAP NEAR PS8461 DIFF=85ohm
DIFF=90ohm
From Nvidia
DIFF=90ohm
Frome Intel
DIFF=85ohm
To eDP Panel CONN
EQ CHECK
Delete
20210310 Knight
20210312 Knight
20210312 Knight
0316 ⍇⺈⺢嬘㕘⡆
0505 min add
0505 min add
3.3VS
3.3VS
3.3VS
3.3VS 1.2VS
1.2VS
1.2VS
1.2VS
3.3VS
3.3VS
3.3VS
3.3VS
CPU_EDP_AUXN 2
CPU_EDP_AUXP 2
DEDP_D_AUX_SCL 28
DEDP_D_AUX#_SDA 28
EDP_HPD 10
DP_TXN0 10
DP_TXP0 10
DP_TXN1 10
DP_TXP1 10
DP_TXP2 10
DP_TXN2 10
DP_TXP3 10
DP_TXN3 10
PS8461_SW 38
CPU_EDP_TXP0 2
CPU_EDP_TXN0 2
CPU_EDP_TXP1 2
CPU_EDP_TXN1 2
CPU_EDP_TXP2 2
CPU_EDP_TXN2 2
CPU_EDP_TXP3 2
CPU_EDP_TXN3 2
DEDP_D0 28
DEDP_D#0 28
SB_IEDP_HPD 38
DEDP_D1 28
DEDP_D#1 28
IN2_HPD 28
PS8461_SW _R 32
DEDP_D2 28
DEDP_D#2 28
DEDP_D3 28
DEDP_D#3 28
SW 1_EDP_AUXP 10
SW 1_EDP_AUXN 10
SMC_BAT 25,49,61,72
SMD_BAT 25,49,61,72
SW 1_IN1_EQ0 49
SW 1_IN1_EQ1 49
SW 1_CFG2 49
Title
Size Document Number Rev
Date: Sheet of
6-71-PC5H0-D02
D02
[35]eDP 2-TO-1 PS8461 SW
A3
35 79 Friday, May 14, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PC50HS-D02
Title
Size Document Number Rev
Date: Sheet of
6-71-PC5H0-D02
D02
[35]eDP 2-TO-1 PS8461 SW
A3
35 79 Friday, May 14, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PC50HS-D02
Title
Size Document Number Rev
Date: Sheet of
6-71-PC5H0-D02
D02
[35]eDP 2-TO-1 PS8461 SW
A3
35 79 Friday, May 14, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PC50HS-D02
R206 4.7K_04
R1525 *4.7K_04
R220 4.7K_04
R1522 4.7K_04
C658
0.
1u_10
V_X5R_04
C1199
1u_6.3V_X5R_04
R1526 *4.7K_04
R878 4.7K_04
C668
0.
1u_10
V_X5R_04
C1226 0.22u_10V_X5R_04
C674
1u_
6.3V
_X5R_04
C1227 0.22u_10V_X5R_04
R871 *4.7K_04
C1234 0.22u_10V_X5R_04
C705
4.
7u_6.
3V_
X
5R_04
C659
0.
1u_10
V_X5R_04
R201 1M_04
R879 *4.7K_04
U60
PS8461E
VDD_DDC
1
VDD33
2
VDDRX12
3
IN1_D0p
4
IN1_D0n
5
I2C_ADDR
6
IN1_D1p
7
IN1_D1n
8
SW
9
IN1_D2p
10
IN1_D2n
11
IN1_D3p
12
IN1_D3n
13
IN2_D0p
14
IN2_D0n
15
IN1_HPD
16
IN2_D1p
17
IN2_D1n
18
IN2_HPD
19
IN2_D2p
20
VDDRX1
2
24
CFG
3
25
CFG
2
26
CFG
1
27
CFG
0
28
VDD3
3
29
PD#
30
REXT
31
VDD1
2
32
CSDA
33
CSCL
34
RSV2
35
RSV1
36
RSV0
37
IN2_EQ0
38
IN2_EQ1
39
IN1_EQ0
40
IN1_EQ1
41
VDDTX12
42
VDDA12
43
OUT_D3n
44
OUT_D3p
45
CFG4
46
OUT_D2n
47
OUT_D2p
48
OUT_HPD
49
OUT_D1n
50
OUT_D1p
51
DP_CADET
52
OUT_D0n
53
OUT_D0p
54
VDDTX12
55
VDD12
56
DP_
A
UXn
_
S
DA
57
DP_
A
UXp
_
S
CL
58
IN
2
_
AUX
n
59
IN
2
_
AUX
p
60
IN
1
_
AUX
n
61
IN2_D2n
21
IN2_D3p
22
IN2_D3n
23
IN
1
_
AUX
p
62
IN
2
_
SDA
63
EP
AD
67
IN
2
_
SCL
64
IN
1
_
SCL
66
IN
1
_
SDA
65
R208
100K_04
R872 4.7K_04
C1218
0.
01u_5
0V_X7
R
_0
4
C673
4.
7u_6.
3V_
X
5R_04
R224 4.7K_04
C1214 0.22u_10V_X5R_04
C704
0.
1u_10
V_X5R_04
C1197
0.
01u_5
0V_X7
R
_0
4
R1520
100K_04
eDP-PANEL
C682
0.
1u_10
V_X5R_04
C680
4.
7u_6.
3V_
X
5R_04
C1237
0.
01u_5
0V_X7
R
_0
4
R866 *100K_04
R877 4.7K_04
.
L6 HCB1608KF-121T30
C1233 0.22u_10V_X5R_04
R1519
100K_04
eDP-PANEL
R200 *4.7K_04
C1248 0.22u_10V_X5R_04
R880
4.99K_1%_04
C1258
0.
01u_5
0V_X7
R
_0
4
R221 *4.7K_04
R199 4.7K_04
R225 *4.7K_04
C1247 0.22u_10V_X5R_04
C1256
0.
01u_5
0V_X7
R
_0
4
C1215
0.
01u_5
0V_X7
R
_0
4
C1235 0.22u_10V_X5R_04
. L8 HCB1608KF-121T30
C1259
0.
01u_5
0V_X7
R
_0
4
R213 *0_04
R882 *0_04
. L11 HCB1608KF-121T30
R226 *4.7K_04
R883 *0_04
C681
0.
1u_10
V_X5R_04
C1229 0.22u_10V_X5R_04
.
L10 HCB1608KF-121T30
C1236 0.22u_10V_X5R_04
C1257
0.
1u_10
V_X5R_04
C1219
0.
01u_5
0V_X7
R
_0
4
R222 4.7K_04
C1216 0.22u_10V_X5R_04
R876 4.7K_04
C1200 0.1u_10V_X7R_04
R207 0_04
C1228 0.22u_10V_X5R_04
C660
4.
7u_6.
3V_
X
5R_04
R873 4.7K_04
C1217 0.22u_10V_X5R_04
R227 *4.7K_04
C1201 0.1u_10V_X7R_04
.
L9 HCB1608KF-121T30
C669
0.
1u_10
V_X5R_04
C1198
0.1u_10V_X5R_04
R223 4.7K_04
R856 *100K_04
R1523 *4.7K_04
C1202 0.1u_10V_X7R_04
R842 0_04
C1246 0.22u_10V_X5R_04
R1521 4.7K_04
C703
0.
1u_10
V_X5R_04
C1238
0.
01u_5
0V_X7
R
_0
4
R881 4.7K_04
R1524 *4.7K_04
C1203 0.1u_10V_X7R_04
C1245 0.22u_10V_X5R_04
C1255 0.22u_10V_X5R_04
C715
4.
7u_6.
3V_
X
5R_04
DEDP_D_AUX_SCL_R
DEDP_D_AUX#_SDA_R
IEDP_AUX#_R
IEDP_AUX_R
DP1_S
W
1
_
R
E
X
T
EDP_HPD_R
SW 1_IN1_EQ1
SW 1_IN1_EQ0
SW 1_IN2_EQ1
SW 1_IN2_EQ0
SW 1_CFG3
SW 1_CFG0
SW 1_CFG1
SW 1_CFG2
SW 1_CFG4
SW 1_EDP_AUXP
I2C_ADDR_SW 1
SW 1_IN1_EQ0
SW 1_IN2_EQ1
SW 1_IN2_EQ0
SW 1_IN1_EQ1
SW 1_EDP_AUXN
MID1_CA_DET
MID1_CA_DET
VDD33_A
VDD33_A
VDD12_A
VDDA12_A
VDDR
X
12_A
VDDRX12_A
VDDTX12_A
VDDTX12_A
VDD33_A
VDD12_A
VDDRX12_A
IEDP_TXP_0_R
IEDP_TXN_0_R
VDDTX12_A
VDDA12_A
IEDP_TXP_1_R
IEDP_TXN_1_R
IEDP_TXP_2_R
IEDP_TXN_2_R
I2C_ADDR_SW 1
EDP_SW _R
IEDP_TXP_3_R
IEDP_TXN_3_R
DEDP_D0_R
DEDP_D#0_R
DEDP_D1_R
DEDP_D#1_R
DEDP_D2_R
DEDP_D#2_R
DEDP_D3_R
DEDP_D#3_R
EDP_SW _R
SW1_CFG3 SW1_CFG2 SW1_CFG1 SW1_CFG0
SW 1_CFG4
VDD12_A CSDA
CSCL
CSCL
CSDA
SW 1_EDP_AUXN
SW 1_EDP_AUXP
RSV0
RSV0
RSV1
RSV2
RSV1
RSV2