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Intel

®

NetStructure

TM

ZT 5515 Compute Processor Board Technical Product Specification

Getting Started

3.6

Switch Options

The ZT 5515 provides several switch configuration options for features that cannot be provided
through the BIOS Setup Utility. Location figures and descriptions are provided in

Chapter 4,

“Configuration.”

3.7

BIOS Configuration Overview

This topic presents an introduction to the ZT 5515’s BIOS. For more detailed information about the
BIOS and other utilities, see the Intel NetStructure Embedded BIOS Manual available on the Intel
Website.

The BIOS has many separately configurable features. These features are selected by running the
built-in Setup utility. System configuration settings are saved in a portion of battery-backed RAM
in the real-time clock device and are used by the BIOS to initialize the system at boot-up or reset.
The configuration is protected by a checksum word for system integrity.

To access the Setup utility, press F2 during the system RAM check at boot-up. When Setup runs,
an interactive configuration screen displays. Refer to

Figure 5, “Setup Screen” on page 27

for an

example.

Setup parameters are divided into different categories. The available categories are listed in a menu
across the top of the Setup screen. The parameters within the highlighted (current) category are
listed in the main (left) portion of the Setup screen. Context sensitive help is displayed in the right
portion of the screen for each parameter. A legend of keys is listed at the bottom of the Setup
screen.

Use the left and right arrow keys to select a category from the menu. Use the up and down arrow
keys to select a parameter in the main portion of the screen. Use the + or – keys to change the value
of a parameter.

Solid arrows next to menu items in the main screen indicate submenus. To display a submenu, use
the up and down arrow keys to highlight the submenu and then press Enter.

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Содержание NetStructure ZT 5515

Страница 1: ...Intel NetStructureTM ZT 5515 Compute Processor Board Technical Product Specification June 2004 Order Number 273813 005 Downloaded from Elcodis com electronic components distributor ...

Страница 2: ...y Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent o...

Страница 3: ...terrupts 18 2 3 14 Counter Timers 19 2 3 15 DMA 19 2 3 16 Real Time Clock 19 2 3 17 Reset 20 2 3 18 Two Stage Watchdog Timer 20 2 3 19 Universal Serial Bus USB 20 2 3 20 Baseboard Management Controller 20 2 3 21 IDE Controller 20 2 3 22 Floppy Disk Controller 21 2 3 23 Keyboard and Mouse Controller 21 2 3 24 LED Indicators 21 2 4 Software 22 3 Getting Started 23 3 1 Unpacking 23 3 2 System Require...

Страница 4: ... 2 Soft Reset Sources 37 5 1 3 Backend Power Down Sources 38 5 1 4 NMI Sources 38 6 System Monitoring and Control 39 6 1 Monitoring and Control Functions 39 6 1 1 Field Replaceable Unit FRU Information 40 6 1 2 System Event Log Information 40 6 2 SMBus Address Map 40 7 IDE Controller 41 7 1 Features of the IDE Controller 41 7 2 Disk Drive Support 41 7 2 1 Primary IDE Channel 41 7 2 2 Secondary IDE...

Страница 5: ...nfiguration 58 9 5 5 Automatic Detection of Video Adapters 58 9 6 BIOS Recovery 58 9 7 Console Redirection 59 9 8 System Management BIOS SMBIOS 59 9 8 1 EN 50081 1 Emissions 91 9 8 2 EN 55024 Immunity 92 9 8 3 FCC USA 92 Figures 1 ZT 5515 Faceplate 12 2 Functional Block Diagram 14 3 Memory Address Map Example 26 4 I O Address Map 26 5 Setup Screen 29 6 Default Switch Configuration 32 7 Watchdog Ti...

Страница 6: ...2 30 J30 COM1 Serial Port Pinout 72 31 J11 PCI Mezzanine Connector Pinout 73 32 J12 PCI Mezzanine Connector Pinout 74 33 J14 PCI Mezzanine Connector Pinout 75 34 J8 IDE Connector Pinout 76 35 Thermal Requirements 77 36 System Register Definitions 79 37 Flash Control 78h 80 38 Watchdog 79h 81 39 PAL Revision ID 7Bh 82 40 Port 80 BIOS POST Codes 80h 82 41 Switch Monitors E3h 83 42 Geographic Address...

Страница 7: ...settings and provides information about tailoring the board to the needs of specific applications Chapter 5 Reset discusses the reset types and reset sources available on the ZT 5515 Chapter 6 System Monitoring and Control lists various system monitoring and control features available on the ZT 5515 Chapter 7 IDE Controller provides an introduction to the ZT 5515 s IDE Controller This chapter cove...

Страница 8: ...ation Document Organization Appendix F Customer Support provides technical and sales assistance information Appendix G Agency Approvals presents UL CE and FCC agency approval and certification information for the ZT 5515 Downloaded from Elcodis com electronic components distributor ...

Страница 9: ... memory and I O technology to provide an inexpensive fast and reliable PICMG 2 16 board The ZT 5515 is CompactPCI Packet Switching Backplane CompactPCI PSB compatible and draws its power from the J1 and J2 connectors but it does not contain a CompactPCI bus The ZT 5515 does include a dual Intelligent Platform Management Bus IPMB for system management along with IPMI v1 5 compatible firmware The ZT...

Страница 10: ... Product Specification Introduction Figure 1 ZT 5515 Faceplate Ejector Handle Ejector Handle PMC Video Ethernet USB CPU Reset Switch COM RS 232 Serial Port IDE Activity LED Reset LED Status LED Hotswap LED Downloaded from Elcodis com electronic components distributor ...

Страница 11: ...000 Mb s Ethernet one available at the faceplate or both at the J3 backplane connector 512 KByte of Level 2 cache 400 MHz front side bus Socketed 256 Mbyte 512 Mbyte or 1 Gbyte of DDR SDRAM memory at 200 or 266 MHz 16 Mbyte of on board flash memory Dual stage watchdog timer Silicon Motion LynxEM on board video IPMI v2 0 firmware available through an Intel Baseboard Management Controller BMC chip O...

Страница 12: ...f the ZT 5515 The following sections provide more detail on the features of the ZT 5515 2 3 1 CompactPCI PSB Architecture The ZT 5515 is designed to operate in a CompactPCI Packet Switching Backplane system CompactPCI PSB though the board does not contain a CompactPCI bus This allows the ZT 5515 to be used in any system master or peripheral slot of a PICMG 2 0 compliant chassis without interfering...

Страница 13: ...tem bus DDR200 266 memory and the latest graphics devices through the 1 5 V AGP4X interface The 82801DB I O Controller Hub ICH4 makes a direct connection to the graphics and memory for faster access to peripherals It provides the features and bandwidth required for applied computing usage models The following is a list of features of the 845E chipset Designed validated and optimized for the Intel ...

Страница 14: ...tarted 2 3 6 Power Ramp Circuitry The ZT 5515 features a power controller with power ramp circuitry that allows the board s voltages to be ramped in a controlled fashion The power ramp circuitry eliminates large voltage or current spikes caused by hot swapping boards This controlled ramping is a requirement of the CompactPCI Hot Swap Specification PICMG 2 1 Version 1 0 see Section D 1 CompactPCI o...

Страница 15: ...video through a Silicon Motion LynxEM ultra low power video chip This device is configured for PCI bus transactions at speeds up to 33 MHz The Lynx chip incorporates 2 Mbyte of integrated SDRAM for the graphics video frame buffer Video signals are available at the ZT 5515 s J25 faceplate connector or at the J5 Rear Panel I O connector see Table 28 J25 VGA Connector Pinout on page 70 and Table 26 J...

Страница 16: ...5515 provides support for two RS 232 compatible serial ports COM1 is accessible at the faceplate through an RJ 45 connector or through the J5 Rear Panel I O connector This port is typically used for test access Both COM1 and COM2 are available at the J5 Rear Panel I O connector No strapping option or software control is required to use either port The front panel serial port is available via a RJ ...

Страница 17: ...cy divider Square wave generator Software triggered Hardware triggered One shot The ZT 5515 s Counter Timers reside in the Intel ICH4 device See Section D 3 Intel 845E Chipset on page 83 for a link to the datasheet for this device 2 3 15 DMA Two cascaded 8237 style DMA controllers are provided on the ZT 5515 for use by the on board peripherals The ZT 5515 s DMA controllers reside in the Intel ICH4...

Страница 18: ...mple code 2 3 19 Universal Serial Bus USB The Universal Serial Bus USB provides a common interface to slower speed peripherals Functions such as keyboard serial ports printer port and mouse ports can be consolidated into USB simplifying cabling requirements The ZT 5515 provides one USB port at its faceplate connector J20 is Port 0 USB Port 1 and USB port 2 are routed to the ZT 5515 s J5 Rear Panel...

Страница 19: ...ler that supports an optional external floppy drive through the PC87417 device Floppy signals are available through the J5 Rear Panel I O connector see Table 26 on page 68 See Section D 6 SuperI O on page 84 for a link to the datasheet for ZT 5515 s I O controller 2 3 23 Keyboard and Mouse Controller The ZT 5515 includes an on board PC AT keyboard controller The ZT 5515 also includes an on board P...

Страница 20: ...erating system from local flash memory CompactFlash a hard drive CD ROM drive or over a network BIOS and firmware updates can be downloaded from the Intel Website The ZT 5515 is compatible with all major PC operating systems including Microsoft Windows 2000 Linux and VxWorks Intel may provide additional drivers for Intel peripherals flash drives and for supported operating systems Software device ...

Страница 21: ...tic free workstation Use the anti static bag shipped with the product to handle the board Wear a wrist strap grounded through one of the system s ESD Ground jacks when servicing system components 3 2 System Requirements The following topics briefly describe the basic system requirements and configurable features of the ZT 5515 Links are provided to other chapters and appendices containing more det...

Страница 22: ...master slot since it has no CompactPCI bus If you are planning on using the CompactPCI bus then you should use a board that is a CompactPCI master in the system master slot such as the Intel NetStructureTM ZT 5504 System Master Processor Board The ZT 5515 is comes with a heatsink that allows the processor to operate between 0 and approximately 50 C ambient with a minimum of 200 LFM 1 meter per sec...

Страница 23: ...ic Industries Alliance at http www eiae org 3 3 Memory Configuration The ZT 5515 components can address up to 4 Gbyte of memory but since the board has only one DIMM socket it can physically only hold up to 1 Gbyte of memory Also there is a lack of manufacturers of single sticks of 2 Gbyte SDRAM DDR unregistered unbuffered ECC non ECC at 200 or 266 MHz The address space is divided between memory l...

Страница 24: ...ol addressed between 780 CF7h PCI Reserved 100h 7FFh decode 11 bits 778 77Fh LPT ECP Registers of address A0h A10h 400 777h Reserved Therefore these peripherals 3F8 3FFh COM1 will alias throughout the 16 bit 3F0 3F7h Floppy IDE Registers I O space at the following 3E0 3EFh Reserved ranges 3B0 3DFh VGA Registers x100 x3FFh 380 3AFh Reserved x500 x7FFh 378 37Fh LPT x900 xBFFh 300 377h Reserved xD00 ...

Страница 25: ...ssor E6 EFh Reserved E1 E5h ZT 5515 System Registers 1 5 E0Fh Reserved C0 DFh On board Slave DMA Controller B4 BFh Reserved B2 B3h APM Registers B0 B1h Reserved A0 AFh On board Slave Interrupt Controller 93 9Fh Reserved 92h Fast RESET and Gate A20 90 91h Reserved 81 8Fh On board DMA Page Registers 80h Diagnostic Port 79h Board s Watchdog Timer Register 78h Board s System Register 0 70 77h On board...

Страница 26: ...tected by a checksum word for system integrity To access the Setup utility press F2 during the system RAM check at boot up When Setup runs an interactive configuration screen displays Refer to Figure 5 Setup Screen on page 27 for an example Setup parameters are divided into different categories The available categories are listed in a menu across the top of the Setup screen The parameters within t...

Страница 27: ...None None None 10 23 01 1 44 1 25MB 3 System Date Legacy Diskette A Primary Master Primary Slave Secondary Master 640 KB F1 ESC Help Exit F9 F10 Setup Defaults Save and Exit Enter Change Values Submenu Select Item Select Menu 64512 KB System Memory Extended Memory Secondary Slave Advanced Power Boot Diagnostics Exit Flash Drive Console Redirection Keyboard Features Select Downloaded from Elcodis c...

Страница 28: ...SETUP boot menu depending on the OS installation media used For example if the OS includes a bootable installation floppy select Removable Media as the first boot device and reboot the system with the installation floppy installed in the floppy drive Note If the installation requires a non bootable CD ROM it is necessary to boot an OS with the proper CD ROM drivers in order to access the CD ROM dr...

Страница 29: ... The switches are listed and briefly described in the Switch Cross Reference table below Factory default switch settings are shown in Figure 6 Default Switch Configuration on page 30 Note Where switches are referenced in this chapter SWX refers to the switch number and N refers to the switch segment SW4 2 means switch number 4 segment 2 Table 3 Switch Cross Reference Table Switch Function SW1 Rese...

Страница 30: ...r and provide a detailed description of each switch 4 2 1 SW1 Reset SW1 is a push button on the front of the ZT 5515 Pressing SW1 issues a hard reset Reset is discussed in more detail in Chapter 5 Reset Figure 6 Default Switch Configuration B0807 01 SW1 J29 SW2 open off 1 2 3 4 SW3 open off 1 2 3 4 SW4 closed on 1 2 3 4 Downloaded from Elcodis com electronic components distributor ...

Страница 31: ... IPMI firmware flash memory Opening the switch allows IPMI firmware updates This switch must be open when using an update utility 4 2 4 SW2 3 Real Time Clock Reset Closing this switch will clear the CMOS real time clock 4 2 5 SW2 4 CMOS Clear Closing this switch will clear the system CMOS This switch is connected to GPIO35 of ICH4 Table 4 SW2 1 Status SW2 1 Function Open Default BIOS on board flas...

Страница 32: ...IPMB power or when power up difficulties are encountered 4 2 8 SW3 3 Ethernet SMBUS isolation Closing this switch will disable the SMBUS connection from BMC to the Ethernet This is used when user want to disable remote management 4 2 9 SW3 4 VGA Routing Control This switch controls the routing of VGA signals to either the front or rear of the board The default switch configuration routes VGA signa...

Страница 33: ...de The BMC on ZT 5515 is able to work as a Baseboard Management Controller or Satellite Management Controller by toggling the SW4 4 Normally the ZT 5515 expects there to be a Baseboard Management Controller on the IPMI bus Flip this switch when you do not have a BMC in the chassis 4 2 13 SW5 Ejector Switch The ejector handles are used when ZT 5515 is inserted or removed hot swapped from a chassis ...

Страница 34: ... numerical order and provide a detailed description of each jumper 4 3 1 J29 BIOS Configuration Mode ZT5515 includes one 3 pin jumper for the purpose of configuring the BIOS Table 14 SW5 Status SW5 Function Open ZT 5515 is a Satellite Management Controller Closed Default ZT 5515 is a Baseboard Management Controller Table 15 J 29 Status J29 Function 1 2 Default Normal operation The BIOS uses its cu...

Страница 35: ...his register are used by the ICH4 to generate a hard reset or a soft reset During a hard reset the ICH4 asserts CPURST PCIRST and RSTDRV Additionally it resets its core and suspend well logic 5 1 2 Soft Reset Sources System Register CF9h ICH4 Reset Control Register Bits 1 and 2 in this register are used by the ICH4 to generate a hard reset or a soft reset During a soft reset the ICH4 asserts INIT ...

Страница 36: ... the board in reset Low Voltage When any of the 3 3 V 5 V or 12 V supply voltages are detected to be below an acceptable operating limit the hot swap controller unconditionally removes backend power and holds the board in reset Overcurrent Fault If a power fault condition overcurrent is detected the hot swap controller removes backend power and turns the Health LED red The board is held in reset 5...

Страница 37: ...onitoring devices are powered from the IPMB Power source allowing the BMC to monitor and control the local CPU without backplane or local power 6 1 Monitoring and Control Functions The BMC tracks the heartbeat of the Host CPU by monitoring several parameters on the ZT 5515 Most of these parameters are measured by the Analog Devices ADM1026 System Monitoring Device Monitoring and control functions ...

Страница 38: ...formation in an 8K x 8 serial EEPROM device Both the in band KCS interface and the out of band IPMB interface provide access to the System Event Log SEL This allows SEL information to be accessed through the IPMB interface even if the system is down 6 2 SMBus Address Map The table below lists the location function and address of each SMBus device used on the ZT 5515 Table 16 SMBus Device Details D...

Страница 39: ...nsfers up to 100 MB sec Individual software control for each IDE channel 32 bit 33 MHz high performance PCI bus interface 7 2 Disk Drive Support The ZT 5515 supports internal and external IDE devices These configurations are described below 7 2 1 Primary IDE Channel The ZT 5515 s primary IDE channel is directed to the J8 IDE connector J8 is used to interface with the locally mounted hard drive For...

Страница 40: ... location on the ZT 5515A 1B the ZT 5515A 1A does not support this CompactFlash carrier on the main board because it does not have an IDE connector This carrier accommodates multiple types of CompactFlash cards which appear to the system as a hard drive and are automatically supported by most operating systems For more information about the ZT 96080 CompactFlash Carrier see the Intel NetStructure ...

Страница 41: ...imer contains a Control and Status Register see Section C 1 2 Watchdog 79h on page 78 for more information The register allows applications to determine if a watchdog timeout caused a particular reset The watchdog timer drives the First and Second Stages as follows 1 The watchdog times out First Stage after a selected timeout interval 2 NMI or INIT software selectable is driven high 3 A hard reset...

Страница 42: ... Watchdog in an Application The following topics are provided to aid you in learning to use watchdog in an application The watchdog s Reset and NMI functions are described and sample code is provided Watchdog Reset and NMI are controlled through the watchdog Control and Status Register See Section C 1 2 Watchdog 79h on page 78 for more information 8 2 1 Watchdog Reset An application using the rese...

Страница 43: ... 0x00 void SetTerminalCount void unsigned char WdValue Holds watchdog register values WdValue inb WD_CSR_IO_ADDRESS Get the current contents of the watchdog register WdValue WD_T_COUNT_MASK Mask out the terminal count bits WdValue WD_500MS_T_COUNT Set the desired terminal count outb WD_CSR_IO_ADDRESS WdValue Furnish the watchdog register with the new count value 8 2 1 3 Strobing the Watchdog Once ...

Страница 44: ... the original NMI ISR vector so that it can be invoked from the new watchdog NMI ISR Alter the interrupt vector table so that the NMI ISR vector is overwritten with a vector to the watchdog ISR C code to do this in DOS might look like the following define NMI_INTERRUPT_VECTOR_NUMBER 2 void interrupt far OldNmiIsr void HookWatchdogIsr void To be absolutely certain the interrupt table is not accesse...

Страница 45: ...his might look like the following define WD_NMI_EN_BIT_SET 0x10 void EnableWatchdogNmi void unsigned char WdValue Holds watchdog register values WdValue inb WD_CSR_IO_ADDRESS Read the current contents of the watchdog register WdValue WD_NMI_EN_BIT_SET Assert the enable bit in the local copy outb WD_CSR_IO_ADDRESS WdValue Assert the enable in the watchdog register Downloaded from Elcodis com electr...

Страница 46: ...ister before taking watchdog related emergency action When the NMI handler completes handling the emergency it invokes the original NMI Handler discussed above The code to do this might look like the following define WD_NMI_DETECT_BIT_SET 0x40 Bit indicates an NMI occurred set void WatchdogIsr void Did the watchdog cause the NMI if inb WD_CSR_IO_ADDRESS WD_NMI_DETECT_BIT_SET TripAlarm Take care of...

Страница 47: ...use the BIOS Recovery Module and FLASH EXE utility available from Intel and discussed later in this chapter The flash memory is write protected through switch SW2 1 See Section 4 2 2 SW2 1 Flash Write Protect on page 31 for more information 9 1 1 Flash Utility Program FLASH EXE is a utility program that comes with the Intel Development Toolkit Run FLASH EXE to modify the BIOS in the on board flash...

Страница 48: ...interactive configuration screen displays Setup parameters are divided into different categories The available categories are listed in a menu across the top of the Setup screen The parameters within the highlighted current category are listed in the main left portion of the Setup screen Context sensitive help is displayed in the right portion of the screen for each parameter A legend of keys is l...

Страница 49: ... FlashID fields statically while a product with several Flash options would need to be able to modify those fields during POST The System Information Structure is defined as follows in C language syntax typedef struct UINT8 Signature 8 UINT32 SysFlag new flags added Ver 1 02 UINT32 BiosAddr UINT32 BiosNvAddr UINT32 FlashAddr UINT16 CPUtype UINT16 BiosSize UINT16 BiosNvSize UINT16 BiosVersion UINT1...

Страница 50: ...ize 40 Size of this table structure in bytes 1 00 StructureVersion 42 Structure Version in BCD Ex 0x0115 for 1 15 See Note 6 1 00 CPUstr 44 A 16 byte ASCII string not zero terminated 1 00 NetworkID 60 CompactNET Network ID See Note 2 1 00 BiosPage 66 BIOS page number if flash is paged See Note 3 1 00 BiosNvPage 67 BIOS NVRAM page number if flash is paged See Note 3 1 00 FlashSize 68 Flash device s...

Страница 51: ...ges This top page is selected by port 0x78 values of 0xf0 through 0xf3 binary 111100xx Any OS image starts at page 0 of flash device 0 or page 0 of flash device 1 if there are two flash devices on board I O port 0x78 is defined as follows Bits 4 7 Page Number Bits 2 3 Flash Device Bit 1 0 Flash write disabled 1 Flash write enable Bit 0 Varies should always be written back with the same value that ...

Страница 52: ...le if the BootBlockSize field is zero then the values in BootBlockAddr and BootBlockPage are invalid and whatever memory space they point to should not be accessed In this case the first block of the flash drive is actually at the top of the flash drive address space directly below the BIOS and other related areas The flash drive area will normally grow downward starting at this block and the logi...

Страница 53: ...t is found the global structure pointer infoptr will be loaded to point to the structure Input None Output return 0 if the structure is found return 1 if the structure is NOT found UNIT8 GetSysInfo void UINT16 i 0 UINT8 __far ptr _FP_SEG ptr 0xf000 _FP_OFF ptr 0 for i 0 i 0xffff SigSIZE i if strncmp ptr i SIGNATURE SigSIZE 0 _FP_SEG infoptr 0xf000 _FP_OFF infoptr i return 0 return 1 It is the appl...

Страница 54: ...s where image will be copied to RAM default 800h UINT32 entry segment offset of execution entry point image default 80 0h UINT16 blocks number of 64K blocks to copy when loading image into RAM UINT16 last number of 16 bit WORDS to copy in last block range 1 8000h UINT32 image_size total image size in bytes not currently used by loader os_header As an example an image of size 94F01h which should be...

Страница 55: ...prior to booting the system Please note that PCI device drivers are required to support the sharing of IRQs Sharing IRQs should not be considered a resource conflict Note that only four legacy IRQs are available for use by PCI devices as a result most of the PCI devices share legacy IRQ s In SMP mode the I O APICs are used instead of the legacy 8259 style interrupt controller There is very little ...

Страница 56: ...for PCI devices to the DOS compatibility hole C0000h to DFFFFh and transfers control to the entry point The DOS compatibility hole is a limited resource so system configurations with a large number of PCI devices may result in a shortage of this resource If the BIOS runs out of option ROM space some PCI option ROMs are not be executed and a POST error is generated Scanning PCI option ROMs may be c...

Страница 57: ...al link COM 1 or COM 2 When console redirection is enabled in BIOS setup local host server keyboard input and video output are passed both to the local keyboard and video connections and to the remote console via the serial link Keyboard inputs from both sources are considered valid and video is displayed to both outputs Optionally the system can be operated without a host keyboard or monitor atta...

Страница 58: ...58 Intel NetStructureTM ZT 5515 Compute Processor Board Technical Product Specification System BIOS This page intentionally left blank Downloaded from Elcodis com electronic components distributor ...

Страница 59: ... specifications Absolute maximum ratings DC operating characteristics Battery backup characteristics A 1 1 Absolute Maximum Ratings The values below are stress ratings only Do not operate the ZT 5515 at these maximums See the DC Operating Characteristics section in this appendix for operating conditions Table 18 Absolute Maximum Ratings Item Absolute Maximum Rating Supply Voltage Vcc 6 5 V Supply ...

Страница 60: ... details on monitoring the processor temperature Table 19 DC Operating Characteristics Item Operating Characteristic Supply Voltage Vcc 4 85 minimum to 5 25 V maximum Supply Voltage Vcc3 3 20 minimum to 3 47 V maximum Supply Voltage AUX 10 8 minimum to 13 2 V maximum Supply Voltage AUX 13 2 minimum to 10 8 V maximum Supply Current Icc 4 5 A average typical with 1 2 GHz processor and 512 Mbyte SDRA...

Страница 61: ...criptions and pinouts A 3 1 Board Dimensions and Weight The ZT 5515 meets the CompactPCI Specification PICMG 2 0 Version 2 1 for all mechanical parameters In a CompactPCI enclosure with 0 8 inch spacing Mechanical dimensions are shown in the PCB Dimensions illustration and are outlined below Table 21 Board Dimensions and Weight Dimension Measurement PCB Dimensions 233 35 mm x 160 mm x 1 6 mm Board...

Страница 62: ...s Connector Function J1 page 65 CompactPCI Bus Connector 110 pin 2 mm x 2 mm female J2 page 66 CompactPCI Bus Connector 110 pin 2 mm x 2 mm female J3 page 67 CompactPCI Ethernet Connector 95 pin 2 mm x 2 mm female J5 page 68 Rear panel I O Connector 110 pin 2 mm x 2 mm female JA1 page 69 Ethernet A Connector 8 pin J25 page 70 VGA Connector 15 pin D Shell J20 page 70 Universal Serial Bus Connector ...

Страница 63: ...63 Specifications Figure 9 Connector Locations J8 IDE J8 IDE J3 Ethernet J5 Rear panel I O J1 CompactPCI Bus J2 CompactPCI Bus J30 COM1 Serial Port JA1 Ethernet A J24 Right Angle DIMM J20 USB J25 VGA J11 J12 J14 PCI Mezzanine Downloaded from Elcodis com electronic components distributor ...

Страница 64: ...emale 32 bit CompactPCI connector AMP 352068 1 Rows 12 14 are used for connector keying See the J1 CompactPCI Bus Connector Pinout table below for pin definitions Refer to Figure 10 above for pin placement Figure 10 Backplane Connectors Pin Locations 11 J1 1 15 25 J3 J5 1 19 1 22 1 22 J2 E D C B A E D C B A Downloaded from Elcodis com electronic components distributor ...

Страница 65: ... 14 GND AD 13 18 SERR GND 3 3V PAR C BE 1 17 3 3V IPMB_CLK IPMB_DATA GND PERR 16 DEVSEL GND V I O STOP LOCK 15 3 3V FRAME IRDY BD_SEL TRDY KEY 11 AD 18 AD 17 AD 16 GND C BE 2 10 AD 21 GND 3 3V AD 20 AD 19 9 C BE 3 IDSEL AD 23 GND AD 22 8 AD 26 GND V I O AD 25 AD 24 7 AD 30 AD 29 AD 28 GND AD 27 6 REQ PCI_PRESENT 3 3V CLK AD 31 5 BRSVP1A5 BRSVP1B5 PCI_RST GND GNT 4 IPMB_PWR HEALTHY V I O INTP INTS ...

Страница 66: ...RT 18 BRSVP2A18 BRSVP2B18 BRSVP2C18 GND BRSVP2E18 17 BRSVP2A17 GND SS_PRST SS_REQ6 SS_GNT6 16 BRSVP2A16 BRSVP2B16 SS_DEG GND BRSVP2E16 15 J2STAGEEN GND SS_FAL SS_REQ5 SS_GNT5 14 AD 35 AD 34 AD 33 GND AD 32 13 AD 38 GND V I O AD 37 AD 36 12 AD 42 AD 41 AD 40 GND AD 39 11 AD 45 GND V I O AD 44 AD 43 10 AD 49 AD 48 AD 47 GND AD 46 9 AD 52 GND V I O AD 51 AD 50 8 AD 56 AD 55 AD 54 GND AD 53 7 AD 59 GN...

Страница 67: ...X3 MDIOBX3 14 VCC3 VCC3 VCC3 VCC VCC 13 PMC IO 1 PMC IO 2 PMC IO 3 PMC IO 4 PMC IO 5 12 PMC IO 6 PMC IO 7 PMC IO 8 PMC IO 9 PMC IO 10 11 PMC IO 11 PMC IO 12 PMC IO 13 PMC IO 14 PMC IO 15 10 PMC IO 16 PMC IO 17 PMC IO 18 PMC IO 19 PMC IO 20 9 PMC IO 21 PMC IO 22 PMC IO 23 PMC IO 24 PMC IO 25 8 PMC IO 26 PMC IO 27 PMC IO 28 PMC IO 29 PMC IO 30 7 PMC IO 31 PMC IO 32 PMC IO 33 PMC IO 34 PMC IO 35 6 PM...

Страница 68: ...T MSDAT MSCLK 14 S1RTS S1CTS S1R1N S1DTR ENETA LINK 13 S1DCD S1TXD S1RXD S1DSR ENETA ACT 12 S2RTS S2CTS S2RIN S2DTR ENETB LINK 11 S2DCD S2TXD S2RXD S2DSR ENETB ACT 10 TRK0 WP RDATA HDSEL DSKCHG 9 MTR1 DIR STEP WDATA WGATE 8 DENSL INDEX MTR0 DR1 DR0 7 CS1S CS3S DA1 RPELED RPEJECT 6 PWRGD SPKR NMI DA0 DA2 5 DDRQ IORDY DIOW DDACK DIOR 4 DD14 DD0 IDE_ACT DD15 DRV IRQ 3 DD3 DD12 DD2 DD13 DD1 2 DD9 DD5 ...

Страница 69: ...out the front JA1 port or out J3 to the backplane Where Ethernet A is routed out the front or the rear is an option in the system BIOS Enter the BIOS Setup screen by pressing F2 while the system is boot through POST A 3 2 6 J25 VGA Connector J25 is a 15 pin female D shell connector AMP 748390 9 providing a front panel interface for VGA signals See the J25 VGA Connector Pinout table for pin definit...

Страница 70: ...erial Port Pinout table below for pin definitions SRI Serial Ring Indicator and SCD Serial Carrier Detect signals are not included in the front panel RJ 45 connector Note COM1 signals are available to the front and rear panel at J5 simultaneously Utilizing COM1 at the front and rear at the same time will cause a signaling conflict Table 28 J25 VGA Connector Pinout Pin Signal Pin Signal Pin Signal ...

Страница 71: ...zanine Connector Pinout Pin Signal Pin Signal 1 NC 2 12V 3 GND 4 B0_INTC 5 B0_INTD 6 B0_INTA 7 NC 8 VCC 9 B0_INTB 10 NC 11 GND 12 NC 13 PMCB_PCICLK 14 GND 15 GND 16 PMC2_GNT 17 PMC2_REQ 18 VCC 19 VIO VCC3 20 B0_PAD31 21 B0_PAD28 22 B0_PAD27 23 B0_PAD25 24 GND 25 GND 26 B0_CBE 3 27 B0_PAD22 28 B0_PAD21 29 B0_PAD19 30 VCC 31 VIO VCC3 32 B0_PAD17 33 B0_FRAME 34 GND 35 GND 36 B0_IRDY 37 B0_DEVSEL 38 V...

Страница 72: ...c PMC2 BUSMODE4 has a 10k pulldown to GND 17 NC 18 GND 19 B0_PAD30 20 B0_PAD29 21 GND 22 B0_PAD26 23 B0_PAD24 24 VCC3 25 PMC2_IDSELd d PMC2_IDSEL is connected to B0_PAD31 PCI device 14h 26 B0_PAD23 27 VCC3 28 B0_PAD20 29 B0_PAD18 30 GND 31 B0_PAD16 32 B0_CBE 2 33 GND 34 NC 35 B0_TRDY 36 VCC3 37 GND 38 B0_STOP 39 B0_PERR 40 GND 41 VCC3 42 B0_SERR 43 B0_CBE 1 44 GND 45 B0_PAD14 46 B0_PAD13 47 GND 48...

Страница 73: ...I O 12 User I O 13 User I O 14 User I O 15 User I O 16 User I O 17 User I O 18 User I O 19 User I O 20 User I O 21 User I O 22 User I O 23 User I O 24 User I O 25 User I O 26 User I O 27 User I O 28 User I O 29 User I O 30 User I O 31 User I O 32 User I O 33 User I O 34 User I O 35 User I O 36 User I O 37 User I O 38 User I O 39 User I O 40 User I O 41 User I O 42 User I O 43 User I O 44 User I O ...

Страница 74: ... 10 DDP11 11 DDP3 12 DDP12 13 DDP2 14 DDP13 15 DDP1 16 DDP14 17 DDP0 18 DDP15 19 GND 20 NC 21 PDREQ 22 GND 23 PDIOW 24 GND 25 PDIOR 26 GND 27 PDIORDY 28 CSEL1a a CSEL1 has 475Ω pulldown to GND 29 PDACK 30 GND 31 IRQ14 32 IOCS16 b b IOCS16 has 10k pullup to VCC3 3 3V 33 DAP1 34 PDIAG 35 DAP0 36 DAP2 37 CS1P 38 CS3P 39 PDASP 40 CS3P 41 VCC 42 VCC 43 GND 44 NC Downloaded from Elcodis com electronic c...

Страница 75: ...and 1 20 V Caution External airflow must be provided at all times during operation to avoid damaging the CPU Intel strongly recommends the use of a fan tray below the card rack to supply the external airflow The Thermal Requirements table below shows the relationship between ambient air temperature board temperature and processor core temperature B 2 Temperature Monitoring Because reliable long te...

Страница 76: ...e of the processor for thermal management purposes When checking airflow conditions let the Processor Core Temperature Test dwell for at least 30 minutes and verify that the core temperature does not exceed 65 C The processor core temperature must never exceed 100 C under any condition of ambient temperature or usage Warning Temperatures over 100 C may result in permanent damage to the processor R...

Страница 77: ...finitions The System Registers are accessible as follows C 1 1 Flash Control 78h Note This register is reset to 00h on init or reset The BIOS resides in page 000 Table 36 System Register Definitions I O Address Register Name Default Value Access Size PAL 78h page 77 Flash Control 0x00 R W 8 bits 79h page 78 Watchdog 0x00 R W 8 bits 7Bh page 80 PAL revision ID 0x00 R W 8 bits 80h page 80 Port 80 0x...

Страница 78: ...ction Controls Write Enable to flash 0 Write protects flash 1 Allows writes to flash Flash memory is discussed in Chapter 9 System BIOS 0 6 4 RESERVED 0 3 Page 3 Flash A23 1Mbyte page 0 2 Page 2 Flash A22 1Mbyte page 0 1 Page 1 Flash A21 1Mbyte page 0 0 Page 0 Flash A20 1Mbyte page 0 I O Address 79h Default Value 0x00 Attribute R W Downloaded from Elcodis com electronic components distributor ...

Страница 79: ...was asserted if bit 3 0 or INIT output was asserted if bit 3 1 Write Value 0 Sets this bit to 0 1 No effect Power Up Value 0 A hard reset will set this bit to 0 3 NMI or INIT Selects between generating an NMI or a CPU INIT Read Value 0 NMI 1 INIT This bit is set to 0 at reset Write Value 0 NMI is generated when the watchdog times out 1 INIT is generated when the watchdog times out Power Up Value 0...

Страница 80: ...L ID I O Address 80h Default Value 0x00 Size 8 bits Attribute WO Table 40 Port 80 BIOS POST Codes 80h Bit Description 7 0 D7 D0 These bits correspond to eight LEDs labeled D0 through D7 on the solder side of the PCB The Port 80 bits report the BIOS POST diagnostic codes These LEDS may not be visible if a hot swap shield is installed on the board D7 corresponds to the most significant bit Address O...

Страница 81: ...roduction testing to load a default CMOS image A logical 1 indicates manufacturing mode A logical 0 indicates non manufacturing mode 3 Reserved 2 Console Redirection Enable This bit reads the status of switch SW4 3 see page 33 A logical 0 means that SW4 3 is open and console redirection is not enabled A logical 1 means SW4 3 is closed and console redirection is enabled Refer to the Console Redirec...

Страница 82: ... board based upon the physical slot into which it was inserted Each backplane connector in a CompactPCI system has a unique code for GA 4 0 See the CompactPCI Specification PICMG 2 0 Version 2 1 for more information on geographic addressing The bits correspond to signals as follows Bit 0 GA0 Bit 1 GA1 Bit 2 GA2 Bit 3 GA3 Bit 4 GA4 A logical 0 indicates that the corresponding GA pin is open A logic...

Страница 83: ... D 2 Ethernet Refer to the Intel 82546EB Dual Port Gigabit Ethernet Controller datasheet for more information on the Ethernet LAN Controller The datasheet is available from Intel s Website at http developer intel com design network products lan controllers 82546 htm D 3 Intel 845E Chipset For more information on the following ZT 5515 functions refer to the Intel 845E datasheet USB Counter Timers D...

Страница 84: ...rganization s Website at http www vita com D 6 SuperI O Refer to the National Semiconductor PC87417 SuperI O Plug and Play Compatible Chip in Compact 100 Pin VLJ Packaging datasheet for more information on the following ZT 5515 functions Floppy Disk controller Serial Port controller Mouse and Keyboard controller Parallel Port The datasheet is available online from the National Semiconductor Websit...

Страница 85: ...esting If the product is found to be otherwise defective Intel at its option will replace or repair the product at no charge except as set forth below provided that you deliver the product along with a return material authorization RMA number see below either to the company from whom you purchased it or to Intel If you ship the product you must assume the risk of damage or loss in transit You must...

Страница 86: ...ect Return Authorization DRA for repair requests e mail address emea fs intel com Intel Business Link IBL http www intel com ibl Telephone No 00 44 1793 403063 Fax No 00 44 1793 403109 Office Hours Monday Friday 0900 1700 UK time E 1 4 For APAC RMA DRA requests email address apac rma front end intel com Telephone No 604 859 3111 or 604 859 3325 Fax No 604 859 3324 Office Hours Monday Friday 0800 1...

Страница 87: ...PRODUCT WHETHER ARISING OUT OF CONTRACT NEGLIGENCE TORT OR UNDER ANY WARRANTY OR FOR INFRINGEMENT OF ANY OTHER PARTY S INTELLECTUAL PROPERTY RIGHTS IRRESPECTIVE OF WHETHER INTEL HAS ADVANCE NOTICE OF THE POSSIBILITY OF ANY SUCH DAMAGES INCLUDING BUT NOT LIMITED TO LOSS OF USE BUSINESS INTERRUPTIONS AND LOSS OF PROFITS NOTWITHSTANDING THE FOREGOING INTEL S TOTAL LIABILITY FOR ALL CLAIMS UNDER THIS ...

Страница 88: ...pport issues please contact your Intel product distributor or Intel Sales Representative for specific information F 2 Sales Assistance If you have a sales question please contact your local Intel NetStructureTM Sales Representative or the Regional Sales Office for your area Address telephone and FAX numbers and additional information is available at Intel s website located at http www intel com ne...

Страница 89: ...2 Safety UL cUL 60950 Safety for Information Technology Equipment UL File E139737 EN IEC 60950 Safety for Information Technology Equipment CB Report Scheme CB certificate and Report G 3 Emissions Test Regulations FCC Part 15 Subpart B EN 55022 CISPR 22 Bellcore GR 1089 9 8 1 EN 50081 1 Emissions GR 1089 CORE Sections 2 and 3 EN 55022 Class A Radiated EN 55022 Power Line Conducted Emissions EN 6100...

Страница 90: ...uipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Note This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 This device may not cause harmful interference 2 This device must accept any interference received including interference that may c...

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