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2. Getting Started

24

Electrical and Environmental

The ZT 5504 requires:

•

+5VDC +5%, -3% @ 4A typical

•

+3.3VDC +5%, -3% @ 6A typical

•

+12VDC ±10% @ 20mA typical

•

-12VDC may be required by a PMC peripheral installed on the ZT 5504.

Configuration 5V

(avg)

5V
(peak)

3.3V
(avg)

3.3V
(peak)

12V
(avg)

12V
(peak)

-12V
(avg)

-12V
(peak)

850MHz 512MB

4A

TBD

6A

TBD

20mA

50mA

0.0A

0.0A

Hard disk (add)
(typical)

540mA

1.00A

N/A N/A N/A N/A N/A N/A

PMC card typical

1

(add)

1.00A 1.70A 0.75A 1.30A 100mA

200mA

20mA 40mA

PMC card max.

2

(add)

1.50A 3.00A 2.25A 4.50A 500mA 500mA 500mA 500mA

Notes:

1. Consult manufacturer of installed PMC card for actual values.
2. In no case shall the total power dissipated by the PMC card exceed 10.0 W.

The ZT 5504 requires 5V V(I/O) to operate as a system master. It supports either 3.3V or 5V
V(I/O) in drone mode. It will not correctly terminate the PCI bus if used in a system slot
configured for 3.3V V(I/O). For this reason, Intel ships the ZT 5504 with a blue key in
CompactPCI connector J1, which prevents the ZT 5504 from being installed in any slot
configured for 3.3V V(I/O).

For the ZT 5504 to be used in drone mode in a peripheral or non-bused slot configured for 3.3V
V(I/O), the key must be removed from J1. The ZT 5504 with the key removed can be used
without damage in a system slot configured for 3.3V V(I/O), but the PCI bus will not operate
correctly. The following table shows ZT 5504 V(I/O) functionality:

Mode V(I/O)

Blue

Key

System Slot – PCI bus in use

5V

Installed

3.3V

Removed

System Slot – PCI bus not in use

5V Installed

3.3V

Removed

Peripheral Slot – Drone mode

5V Installed

3.3V

Removed

Non-Bused Node Slot – Drone mode

5V Installed

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Содержание NetStructure ZT 5504

Страница 1: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

Страница 2: ...Intel NetStructure ZT 5504 System Master Processor Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 3: ...y intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any ex...

Страница 4: ...7 PCI Video 17 PCI Mezzanine Card PMC Interface 18 Dual Ethernet Interfaces 18 IDE Hard Drive 18 Serial I O 18 Interrupts 19 Counter Timers 19 DMA 20 Real Time Clock 20 Reset 20 Two Stage Watchdog Tim...

Страница 5: ...ect 33 SW3 3 IPMI Flash Write Protect 34 SW3 4 Drone Mode Reset 34 SW4 1 SW4 2 SW4 3 Software Configuration 34 SW4 4 Console Redirection 34 Cuttable Trace Options and Locations 35 CT14 CT15 CT17 19 CT...

Страница 6: ...Using the Watchdog in an Application 47 Watchdog Reset 47 Enabling the Watchdog Reset 47 Setting the Terminal Count 48 Strobing the Watchdog 48 Watchdog NMI 48 Chaining the ISRs 49 Enabling the Watchd...

Страница 7: ...equirements 67 Temperature Monitoring 68 C System Registers 69 System Register Definitions 69 Flash Control 78h 70 Watchdog 79h 71 J1 IPMB Control 7Bh 74 Port 80 BIOS POST Codes 80h 74 Event Monitors...

Страница 8: ...issions 80 EN 55024 Immunity 80 Regulatory Information 81 FCC USA 81 Industry Canada Canada 81 F Customer Support 82 Technical Support and Return for Service Assistance 82 Sales Assistance 82 Artisan...

Страница 9: ...out 60 J5 Rear Panel I O Connector Pinout 61 JA4 and J17 Ethernet A and B Connector Pinout 62 J6 VGA Connector Pinout 62 J8 and J9 Universal Serial Bus 0 and 1 Connector Pinout 63 J10 COM1 Serial Port...

Страница 10: ...etup Screen 29 Default Switch Configuration 32 Cuttable Trace Locations 36 Watchdog Timer Architecture 46 BIOS Recovery Socket Location 51 PCB Dimensions 55 Connector Locations 57 Backplane Connectors...

Страница 11: ...Chapter 6 IDE Controller provides an introduction to the ZT 5504 s IDE Controller This chapter covers drive configuration IDE I O mapping device drivers and the ZT 5504 s support for internal and exte...

Страница 12: ...ZT 5504 includes CompactPCI Packet Switching Backplane CompactPCI PSB compliance and Intelligent Platform Management Bus IPMB system management features The ZT 5504 CPU board is an ideal solution for...

Страница 13: ...tive Ejector Handle with Hot Swap Switch Ejector Handle Video J6 PMC Slot USB 0 and 1 J8 and J9 Reset Push button SW 1 COM Port J10 System LEDs Features CompactPCI Specification PICMG 2 0 Version 2 1...

Страница 14: ...Mbit s Ethernet available at the faceplate or the J3 backplane connector Primary IDE channel supports the on board 2 5 inch hard disk and an IDE device CD ROM on a media expansion board Single on boar...

Страница 15: ...to PCI Bridge Interface IDE HARD DRIVE Floppy Disk Controller Serial Number Temp Sensor Watchdog Timer BGA2 Flash Memory BIOS CompactPCI PSB Architecture The ZT 5504 is designed to operate in a Compac...

Страница 16: ...m III processor also operates with a 100 MHz Processor Side Bus for faster access to memory and data The Mobile Pentium III Processor M in BGA2 Package topic in Appendix E contains a link to the datas...

Страница 17: ...he board is operating in isolation from the backplane CAUTION The ZT 5504 is not intended to be hot swapped in the system slot Hot swapping the CPU board in the system slot may damage other boards in...

Страница 18: ...e signals are available for use by a rear panel transition board such as the ZT 4807 Serial ports COM1 and COM2 USB Ports 0 and 1 through cuttable trace configuration Floppy Interface Keyboard PS 2 mo...

Страница 19: ...the J3 backplane connector See Geographic Addressing E4h in Appendix C for more information The Ethernet topic in Appendix E contains links to the datasheets for the Ethernet devices used on the ZT 5...

Страница 20: ...isk IDE interface Real Time Clock CompactPCI backplane 21154 On board PCI devices Enhanced capabilities include the ability to configure each interrupt level for active high going edge or active low l...

Страница 21: ...timer optionally monitors system operation and is programmable for one of eight different timeout periods from 0 25 seconds to 256 seconds It is a two stage watchdog meaning that it can be enabled to...

Страница 22: ...r for more information on the ZT 5504 s IDE controller The ZT 5504 s IDE controller resides in the Intel 82371EB PIIX4E device The Intel 440GX AGPset topic in Appendix E provides a link to the datashe...

Страница 23: ...stem from local flash memory a hard drive CD ROM drive or over a network BIOS and firmware updates can be downloaded from the Intel Website The ZT 5504 is compatible with all major PC operating system...

Страница 24: ...ration the ZT 5504 must run Intel NetStructure Embedded BIOS v5 x revision C01 or P01 and later P01 Pxx The revision level is shown in the BIOS Identification string displayed during the Power On Self...

Страница 25: ...3 3V or 5V V I O in drone mode It will not correctly terminate the PCI bus if used in a system slot configured for 3 3V V I O For this reason Intel ships the ZT 5504 with a blue key in CompactPCI con...

Страница 26: ...core temperature must never exceed 100 C under any condition of ambient temperature or usage This may result in permanent damage to the processor The ZT 5504 may contain materials that require regulat...

Страница 27: ...PHERALS 100000h 1FFFFFFFh SYSTEM MEMORY 4 GB 512 KB 512 MB 1 MB E0000h FFFFFh SYSTEM BIOS C8000h DFFFFh BIOS EXTENSION C0000h C7FFFh VGA BIOS A0000h BFFFFh VGA DISPLAY MEMORY 0h 9FFFFh LOCAL DRAM 896...

Страница 28: ...rs decoding is used for the 178 1DFh Reserved onboard ISA devices 170 177h Secondary IDE Registers 100 16Fh Reserved F0 FFh Coprocessor E6 EFh Reserved E1 E5h ZT 5504 System Registers 1 5 E0Fh Reserve...

Страница 29: ...are saved in a portion of battery backed RAM in the real time clock device and are used by the BIOS to initialize the system at boot up or reset The configuration is protected by a checksum word for...

Страница 30: ...equire initial installation on a hard drive from a floppy or CD ROM drive These devices should be configured installed and tested with the supplied drivers before attempting to load the new operating...

Страница 31: ...odes of Intel products 6 When installation is complete reboot the system and set the boot device order in the SETUP boot menu appropriately 7 The Flash Write Protect Write Enable switch SW3 2 must be...

Страница 32: ...he board The switches are listed and briefly described in the Switch Cross Reference table below Factory default switch settings are shown in the Default Switch Settings figure Note Where switches are...

Страница 33: ...in Chapter 4 SW2 1 SW2 2 Real Time Clock Battery Backup Use these switch segments to battery back and clear the Real Time Clock When closed SW2 1 connects the Real Time Clock to the on board battery...

Страница 34: ...ecovery Socket U38 When SW3 1 is open the BIOS boots from the on board flash memory When SW3 1 is closed the BIOS boots from the BIOS Recovery Socket Factory default is open See the BIOS Recovery Modu...

Страница 35: ...are Configuration These switch segments provide configuration information to the user s software The Switch Monitor register Port E3h Bits 0 3 monitors the status of SW4 segments as listed below An op...

Страница 36: ...tween one set of pads depending on the chosen option CAUTION The ZT 5504 has additional cuttable traces not documented in this manual These should not be modified by the user Modifications to document...

Страница 37: ...rear routing Cuttable Trace Locations Secondary Side CT24 ENET B CT21 ENET A CT23 R EJ CT19 VIDEO CT14 KBD MS CT28 ID 2 CT16 ID 0 CT27 ID 3 CT29 ID 1 CT15 USB0 CT22 USB1 CT18 COM1 CT17 L EJ CT51 SW1...

Страница 38: ...2 USB1 Front Rear Routing CT31 and CT32 determine the routing for USB channel 1 The A position default routes USB1 to J9 at the front panel The B position routes USB1 to Rear Panel I O connector J5 Th...

Страница 39: ...to prevent glitching of the RS 232 interface as the ZT 5504 comes out of reset The factory default installs CT36 CT38 Function In Default Disable RS 232 driver during board reset Out Enable RS 232 dr...

Страница 40: ...the ZT 5504 s faceplate to issue a system reset System Register CF9h PIIX4E Reset Control Register Bits 1 and 2 in this register are used by the PIIX4E to generate a hard reset or a soft reset During...

Страница 41: ...ditionally removes backend power from the board and holds the board in reset Low Voltage When any of the 3 3V 5V or 12V supply voltages are detected to be below an acceptable operating limit the hot s...

Страница 42: ...The BMC tracks the heartbeat of the Host CPU by monitoring several parameters on the ZT 5504 Most of these parameters are measured by the Analog Devices ADM1026 System Monitoring Device Monitoring an...

Страница 43: ...ard if present Each device has its own address System Event Log Information The BMC controller stores system event information in an 8K x 8 serial EEPROM device Both the in band KCS interface and the...

Страница 44: ...Replaceable Unit SEEPROM 1010 010 SEL System Event Log SEEPROM 1010 011 Signal Presence Detect SPD PROM in Bank 1 1010 000 SDRAM Banks 1 and 2 Signal Presence Detect SPD PROM in Bank 2 1010 001 CY2310...

Страница 45: ...ftware control for each IDE channel 32 bit 33 MHz high performance PCI bus interface Disk Drive Support The ZT 5504 supports internal and external IDE devices These configurations are described below...

Страница 46: ...ve and are automatically supported by most operating systems For more information about the ZT 96080 CompactFlash Carrier see the Intel NetStructure building blocks page at http developer intel com de...

Страница 47: ...he ZT 5504 s custom watchdog timer circuit is implemented in a programmable logic device The watchdog timer contains a Control and Status Register which is documented in Appendix C as Watchdog 79h The...

Страница 48: ...atchdog s Reset and NMI functions are described and sample code is provided Watchdog Reset and NMI are controlled through the watchdog s Control and Status Register documented in Appendix C as Watchdo...

Страница 49: ...OUNT Set the desired terminal count outb WD_CSR_IO_ADDRESS WdValue Furnish the watchdog register with the new count value Strobing the Watchdog Once the watchdog is enabled it must be periodically str...

Страница 50: ...e installing the new vector Install the new ISR oldNmiIsr getvect IsrVector Save the old vector setvect NMI_INTERRUPT_VECTOR_NUMBER WatchdogIsr Install the new Enabling the Watchdog NMI To activate th...

Страница 51: ...e NMI handler completes handling the emergency it invokes the original NMI Handler discussed above The code to do this might look like the following define WD_NMI_DETECT_BIT_SET 0x40 Bit indicates an...

Страница 52: ...ash device is divided into 8 pages mapped into a window in extended memory FFF80000h FFFFFFFFh The BIOS occupies 512 KB in flash page 0 To reprogram the BIOS or update it if it becomes corrupted use t...

Страница 53: ...sabled SW3 2 open 4 Re insert the board in the enclosure and power on the board The system should boot 5 See the Flash Utility Program topic below for detailed instructions on reprogramming the on boa...

Страница 54: ...e stress ratings only Do not operate the ZT 5504 at these maximums See the DC Operating Characteristics section in this appendix for operating conditions Supply Voltage Vcc 6 5V Supply Voltage Vcc3 4...

Страница 55: ...tery is not field replaceable There is a danger of explosion if the battery is incorrectly replaced or handled Do not disassemble or recharge the battery Do not dispose of the battery in fire When the...

Страница 56: ...cation PICMG 2 0 Version 2 1 for all mechanical parameters In a CompactPCI enclosure with 0 8 inch spacing Mechanical dimensions are shown in the PCB Dimensions illustration and are outlined below PCB...

Страница 57: ...m female J2 CompactPCI Bus Connector 110 pin 2 mm x 2 mm female J3 CompactPCI Connector 95 pin 2 mm x 2 mm female J5 Rear panel I O Connector 110 pin 2 mm x 2 mm female JA4 Ethernet A Connector 8 pin...

Страница 58: ...J16 PMC J14 Primary IDE J9 J8 J6 J17 JA4 VGA ENETB ENETA USB1 USB0 J13 PMC Backplane Connectors Pin Locations 11 J1 1 15 25 J3 J5 1 19 1 22 1 22 J2 E D C B A E D C B A Artisan Technology Group Qualit...

Страница 59: ...PAR C BE 1 17 3 3V IPMB_CLK IPMB_DATA GND PERR 16 DEVSEL GND V I O STOP LOCK 15 3 3V FRAME IRDY BD_SEL TRDY GROUND KEY 11 AD 18 AD 17 AD 16 GND C BE 2 10 AD 21 GND 3 3V AD 20 AD 19 9 C BE 3 IDSEL AD 2...

Страница 60: ...17 BRSVP2A17 GND SS_PRST SS_REQ6 SS_GNT6 16 BRSVP2A16 BRSVP2B16 SS_DEG GND BRSVP2E16 15 J2STAGEEN GND SS_FAL SS_REQ5 SS_GNT5 14 AD 35 AD 34 AD 33 GND AD 32 13 AD 38 GND V I O AD 37 AD 36 12 AD 42 AD...

Страница 61: ...C NC NC 18 RP_TXA RP_TXA GND NC NC 17 RP_RXA RP_RXA GND NC NC 16 RP_TXB RP_TXB GND NC NC 15 RP_RXB RP_RXB GND NC NC 14 NC NC NC NC NC 13 NC NC NC NC NC 12 NC NC NC NC NC 11 NC NC NC NC NC 10 NC NC NC...

Страница 62: ...ND V SYNC GND SMBA 17 GND RSVD RPIO_PRESENT RSVD IPMB_PWR 16 BLUE GND DDCCLK KBDAT KBCLK 15 GND SW 5V DDCDAT MSDAT MSCLK 14 S1RTS S1CTS S1R1N S1DTR ENETA LINK 13 S1DCD S1TXD S1RXD S1DSR ENETA ACT 12 S...

Страница 63: ...nd J17 Ethernet A and B Connector Pinout Pin Function 1 TX 2 TX 3 RX 4 Unused 5 Terminated on ZT 5504 6 RX 7 Unused 8 Terminated on ZT 5504 J6 VGA Connector J6 is a 15 pin female D shell connector AMP...

Страница 64: ...2 DATA 3 DATA 4 GND J10 COM1 Serial Port J10 is an RJ 45 connector providing a front panel COM1 interface COM1 signals are also directed out J5 to the backplane See the J10 COM1 Serial Port Pinout tab...

Страница 65: ...INTA 7 NC 8 VCC 9 B0_INTB 10 NC 11 GND 12 NC 13 PMCB_PCICLK 14 GND 15 GND 16 PMC2_GNT 17 PMC2_REQ 18 VCC 19 VIO VCC3 20 B0_PAD31 21 B0_PAD28 22 B0_PAD27 23 B0_PAD25 24 GND 25 GND 26 B0_CBE 3 27 B0_PAD...

Страница 66: ...1 BO PAD16 32 B0_CBE 2 33 GND 34 NC 35 B0_TRDY 36 VCC3 37 GND 38 B0_STOP 39 B0_PERR 40 GND 41 VCC3 42 B0_SERR 43 B0_CBE 1 44 GND 45 B0_PAD14 46 B0_PAD13 47 GND 48 B0_PAD10 49 B0_PAD8 50 VCC3 51 B0_PAD...

Страница 67: ...6 6 DDP9 7 DDP5 8 DDP10 9 DDP4 10 DDP11 11 DDP3 12 DDP12 13 DDP2 14 DDP13 15 DDP1 16 DDP14 17 DDP0 18 DDP15 19 GND 20 NC 21 PDREQ 22 GND 23 PDIOW 24 GND 25 PDIOR 26 GND 27 PDIORDY 28 CSEL1 1 29 PDACK...

Страница 68: ...The maximum power dissipation of the CPU is 21 W at 850 MHz and 1 60V CAUTION External airflow must be provided at all times during operation to avoid damaging the CPU Intel strongly recommends the us...

Страница 69: ...includes an AMD 1026 Hardware Monitor to monitor the die temperature of the processor for thermal management purposes When checking airflow conditions let the Processor Core Temperature Test dwell for...

Страница 70: ...nder their control System Register Definitions The System Registers are accessible as follows I O Address Register Name Default Value Access Size 78h Flash Control 0x00 R W 8 bits 79h Watchdog 0x00 R...

Страница 71: ...lash memory is discussed in Chapter 8 BIOS Recovery 0 6 BIOS Recovery Module Access Override Controls flash access to the BIOS Recovery Module The BIOS Recovery Module is discussed in Chapter 8 0 Allo...

Страница 72: ...o 0 1 No effect Power Up Value 0 A hard reset not caused by a watchdog timeout will set this bit to 0 6 Stage 1 Monitor NMI or INIT Monitor Monitors the first stage NMI or INIT timer status Read Value...

Страница 73: ...t to 0 4 Stage 1 Enable Enables NMI or INIT activation on timeout Read Value 0 Disabled 1 Enable NMI activation on timeout if bit 3 0 Enable INIT activation on timeout if bit 3 1 Write Value 0 Disable...

Страница 74: ...0 Terminal Count TermCnt2 TermCnt0 Read Value Reflects the value written to bits 2 through 0 Write Value These bits determine the terminal count of the watchdog Below is the minimum timeout period Th...

Страница 75: ...nected to J1 3 0 RESERVED Port 80 BIOS POST Codes 80h I O Address 80h Default Value 0x00 Size 8 bits Attribute WO Bit Description 7 0 D7 D0 These bits correspond to eight LEDs labeled D0 through D7 on...

Страница 76: ...is bit corresponds to the status of switch SW3 2 A logical 0 means that the flash is write protected by SW3 2 a logical 1 means the flash is not write protected by SW3 2 6 System Enable This bit corre...

Страница 77: ...he bits correspond to switch segments as follows Bit 0 SW4 1 Bit 1 SW4 2 Bit 2 SW4 3 Geographic Addressing E4h Address Offset E4h Default Value 0x00 Size 8 bits Attribute RO Bit Description 7 Ethernet...

Страница 78: ...formation on geographic addressing The bits correspond to signals as follows Bit 0 GA0 Bit 1 GA1 Bit 2 GA2 Bit 3 GA3 Bit 4 GA4 A logical 0 indicates that the corresponding GA pin is open A logical 1 i...

Страница 79: ...Website at http www picmg org Ethernet Refer to the Intel 82550 Fast Ethernet Multifunction PCI Cardbus Controller datasheet for more information on the Ethernet LAN Controller The datasheet is availa...

Страница 80: ...ion refer to the sponsoring organization s Website at http www vita com SuperI O Refer to the National Semiconductor PC87309 SuperI O Plug and Play Compatible Chip in Compact 100 Pin VLJ Packaging dat...

Страница 81: ...15 Subpart B EN 55022 CISPR 22 Bellcore GR 1089 EN 50081 1 Emissions GR 1089 CORE Sections 2 and 3 EN 55022 Class A Radiated EN 55022 Power Line Conducted Emissions EN 61000 3 2 Power Line Harmonic E...

Страница 82: ...peration is subject to the following two conditions 1 This device may not cause harmful interference 2 This device must accept any interference received including interference that may cause undesired...

Страница 83: ...Representative for specific information Sales Assistance If you have a sales question please contact your local Intel NetStructure Sales Representative or the Regional Sales Office for your area Addre...

Страница 84: ...service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE IN...

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