2:44
Volume 2, Part 1: System State and Programming Model
3.4
Processor Virtualization
Processors in the Itanium Processor Family may optionally implement a mechanism to
support processor virtualization. This includes an additional PSR.vm bit (see
3.3.2, “Processor Status Register (PSR)”
), which, when 1, causes certain instructions to
take a Virtualization fault (see
Section 5.6, “Interruption Priorities”
vector (0x6100)” on page 2:209
The set of instructions which are virtualized by PSR.vm are listed in
below.
Processors which support processor virtualization must provide an
implementation-dependent mechanism for disabling the
vmsw
instruction. When
enabled, the
vmsw
instruction functions as described on the
vmsw
instruction page.
When disabled, the
vmsw
instruction always raises a Virtualization fault when executed
at the most privileged level.
Processors which support processor virtualization may provide an
implementation-dependent mechanism to disable virtual machine features, see
“PAL_PROC_GET_FEATURES – Get Processor Dependent Features (17)” on page 2:446
for details.
Processor virtualization is largely invisible to system software, and therefore its effects
on virtualized instructions are not discussed in this document, except on the instruction
description pages themselves.
§
Table 3-10.
Virtualized Instructions
Class
Virtualized Instructions
All privileged instructions
itc.i, itc.d, itr.i, itr.d, ptc.l, ptc.g, ptc.ga, ptc.e, ptr,
tak, tpa, mov rr, mov pkr, mov cr, mov ibr, mov dbr, mov pmc,
mov to pmd, ssm, rsm, mov psr, rfi, bsw
Some non-privileged
instructions (virtualized at
all privilege levels)
thash, ttag, mov from cpuid, probe
a
a. Virtualization of the
probe
instruction is configurable, see
Section 11.7.4.2.8, “Probe Instruction
for details.
Some non-privileged
instructions (virtualized at
privilege level 0)
Reading AR[ITC] or
AR[RUC] with PSR.si==1
(virtualized at all privilege
levels)
mov from ar.itc, mov from ar.ruc
Instructions which write
privileged registers
mov to ar.itc, mov to ar.ruc
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
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Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
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Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
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Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
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Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...