
Volume 2, Part 1: System State and Programming Model
2:41
3.3.5.7
Interruption Function State (IFS – CR23)
The IFS register is used to reload the current register stack frame (CFM) on a Return
From Interruption (
rfi
). If the IFS is accessed while PSR.ic is 1, an Illegal Operation
fault is raised. The IFS can only be accessed at privilege level 0; otherwise, a Privileged
Operation fault is raised. The IFS.v bit is cleared on interruption if PSR.ic is 1. All other
fields are undefined after an interruption. If PSR.ic is 0, the
cover
instruction copies
CFM to IFS.ifm and sets IFS.v to 1. See
for the IFS field
definitions.
3.3.5.8
Interruption Immediate (IIM – CR24)
) records the zero-extended immediate field encoded
in
chk.a
,
chk.s
,
fchkf
or
break
instruction faults. The
break.b
instruction always
writes a zero value and ignores its immediate field. The IA_32_Intercept vector writes
all 64-bits of IIM to indicate the cause of the intercept. See
the value of IIM in other situations. For the purpose of resource dependency, IIM is
written as a result of the fault, not by the instruction itself.
3.3.5.9
Interruption Hash Address (IHA – CR25)
The IHA (
) is loaded with the address of the Virtual Hash Page Table (VHPT)
entry the processor referenced or would have referenced to resolve a translation fault.
The IHA is written on interruptions by the processor when PSR.ic is 1. Refer to
for complete details. See
for the value
of IHA in other situations. All upper 62 address bits of IHA must be implemented
regardless of the size of the virtual address space supported by the processor model
(see
“Unimplemented Address Bits” on page 2:73
). The virtual address written to IHA
by the processor is guaranteed to be an implemented virtual addresses on all processor
models; however, if the address referenced by the VHPT is an unimplemented virtual
address, the value of IHA is undefined.
Figure 3-14. Interruption Function State (IFS – CR23)
63 62
38 37
0
v
rv
ifm
1
25
38
Table 3-9.
Interruption Function State Fields
Field
Bits
Description
ifm
37:0
Interruption Frame Marker
v
63
Valid bit, cleared to 0 on interruption if PSR.ic is 1.
rv
62:38
reserved
Figure 3-15. Interruption Immediate (IIM – CR24)
63
0
Interruption Immediate
64
Figure 3-16. Interruption Hash Address (IHA – CR25)
63
2
1
0
Interruption Hash Address
ig
62
2
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Страница 1: ......
Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Страница 230: ......
Страница 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
Страница 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Страница 891: ......
Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Страница 1296: ......
Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...