Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 321 / 1898

Volume 2, Part 1: Addressing and Protection 2:73
4.2 Physical Addressing
Objects in memory and I/O occupy a common 63-bit physical address space that is
accessed using byte addresses. Accesses to physical memory and I/O may be
performed via virtual addresses mapped to the 63-bit physical address space or by
direct physical addressing. Current page table formats allow for mapping virtual
addresses into 50 bits of physical address space (on processor implementations that
support this many physical address bits). Future extensions to the page table formats
will allow larger mappings, up to the full 63 bits of physical address space.
Physical addressing for instruction references (including IA-32) is enabled when PSR.it
is 0, data references (including IA-32) when PSR.dt is 0, and register stack references
when PSR.rt is 0.
While software views the physical addressing as being 63-bits, implementations may
implement between 32 and 63 physical address bits. All processor models must
implement a contiguous set of physical address bits starting at bit 32 and continuing
upwards. Please see the processor-specific documentation for further information on
the number of physical address bits implemented on the Itanium processor.
Implementations must validate that memory references are performed to implemented
physical address bits. Instruction references to unimplemented physical addresses
result either in an Unimplemented Instruction Address trap on the last valid instruction,
or in an Unimplemented Instruction Address fault on the instruction fetch of the
unimplemented address. Data references to unimplemented physical addresses result
in an Unimplemented Data Address fault. Memory references to unpopulated address
ranges result in an asynchronous Machine Check abort, when the platform signals a
transaction time-out. Exact machine check behavior is model specific.
4.3 Unimplemented Address Bits
Based on the processor model, some physical and/or virtual address bits may not be
implemented. Regardless of the number of implemented address bits, all general
purpose, branch, control and application registers implement all 64 register bits on all
processors. Similarly, regardless of the number of implemented address bits, data and
instruction breakpoint registers must implement all 64 address bits and all 56 mask bits
on all processors.
4.3.1 Unimplemented Physical Address Bits
As shown in Figure 4-18 , a 64-bit physical address consists of three fields: physical
memory attribute (PMA), unimplemented and implemented bits.
All processor models implement at least 32 physical address bits, bits 0 to 31, plus the
physical memory attribute bit. Additional implemented physical bits must be contiguous
starting at bit 32. IMPL_PA_MSB is the implementation-specific position of the most
Figure 4-18. Physical Address Bit Fields
63 62 IMPL_PA_MSB 0
PMA unimplemented implemented
1 62 - IMPL_PA_MSB IMPL_ 1