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DKHiQV-AGP (Fab. Rev. A) User’s Guide
&+,36
DKHiQV-AGP (Fab. Rev. A) Subject to Change Without Notice
Revision 1.0 7/13/98
3.3
Display Interface
3.3.1
CRT Display Interface
The DK Board provides direct interface to analog CRTs through an industry standard 15-pin connector (J4).
3.3.2
Flat Panel Display Interface
The DKHiQV-AGP board has a 50-pin connector (J5) which provides all necessary signals to interface with
any flat panel having a data word size of 24 bits or less (see figure 1). The HiQVideo
controller has enough
drive for most panels and does not require any buffering on connectors J5 and J11.
The HiQVideo
Series controllers provide 8mA drive on all data and control signals (FR0A[2] must be set
to 1 when DVCC = 3.3V). A second connector (J11) provides the 12 additional data bits needed for 36-bit
panels (see Figure2). Table 2 has a summary for all panel interface connections.
3.3.3
STN-DD Buffer
STN-DD panels require video data alternating between two separate locations in memory. In addition, a
dual-drive panel requires data from both locations simultaneously. These operations require a frame stor-
age area, called a ’STN-DD buffer’. The HiQVideo
controller’s innovative architecture implements the
STN-DD buffer in an unused area of display memory, reducing chip count and video subsystem cost. The
embedded STN-DD buffer may be enabled by setting FR1A[0,7]=1,0.
Figure 1. shows the 24 bit panel pin assignments for the J5 connector:
Figure 1: 24 Bit Flat Panel Connector Pinout
Name
Pin #
Pin #
Name
[+5V]
VDDSAFE
1
2
+12 VSAFE
(12 to 45V) or (-12 to -45V)
VEESAFE
3
4
nc or DVCC55X (see JP4)
ENABKL
5
6
GND
M
7
8
DE
GND
9
10
LP
FLM
11
12
GND
SNFCLK
13
14
GND
P0
15
16
P1
GND
17
18
P2
P3
19
20
GND
P4
21
22
P5
GND
23
24
P6
P7
25
26
GND
P8
27
28
P9
GND
29
30
P10
P11
31
32
GND
P12
33
34
P13
GND
35
36
P14
P15
37
38
GND
P16
39
40
P17
GND
41
42
P18
P19
43
44
GND
P20
45
46
P21
GND
47
48
P22
P23
49
50
GND
