Intel BX80623I32100, Техническое описание

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Datasheet, Volume 1 23
Interfaces
2.1.5 Technology Enhancements of Intel
®
Fast Memory Access
(Intel
®
FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1 Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2 Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3 Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6 Memory Type Range Registers (MTRRs) Enhancement
The processor has 2 additional MTRRs (total 10 MTRRs). These additional MTRRs are
specially important in supporting larger system memory beyond 4 GB.
2.1.7 Data Scrambling
The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the
data bus. Past experience has demonstrated that traffic on the data bus is not random
and can have energy concentrated at specific spectral harmonics creating high di/dt
that is generally limited by data patterns that excite resonance between the package
inductance and on-die capacitances. As a result, the memory controller uses a data
scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce
the impact of any excessive di/dt.