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Signal Descriptions

Datasheet

DDR{0/1/2}_MA[15:0]

Selects the Row address for Reads and writes, and the column address for

activates. Also used to set values for DRAM configuration registers.

DDR{0/1/2}_ODT[3:0]

Enables various combinations of termination resistance in the target and non-

target DIMMs when data is read or written

DDR{0/1/2}_RAS#

Row Address Strobe.

DDR{0/1/2}_RESET#

Resets DRAMs. Held low on power up, held high during self refresh, otherwise

controlled by configuration register.

DDR{0/1/2}_WE#

Write Enable.

ISENSE

Current sense from VRD11.1.

PECI

I/O

PECI (Platform Environment Control Interface) is the serial sideband interface to

the processor and is used primarily for thermal, power and error management.

Details regarding the PECI electrical specifications, protocols and functions can

be found in the Platform Environment Control Interface Specification.

PRDY#

PRDY# is a processor output used by debug tools to determine processor debug

readiness.

PREQ#

I/O

PREQ# is used by debug tools to request debug operation of the processor.

PROCHOT#

I/O

PROCHOT# will go active when the processor temperature monitoring sensor

detects that the processor has reached its maximum safe operating

temperature. This indicates that the processor Thermal Control Circuit has been

activated, if enabled. This signal can also be driven to the processor to activate

the Thermal Control Circuit. This signal does not have on-die termination and

must be terminated on the system board.

PSI#

Processor Power Status Indicator signal. This signal is asserted when maximum

possible processor core current consumption is less than 20A. Assertion of this

signal is an indication that the VR controller does not currently need to be able

to provide ICC above 20A, and the VR controller can use this information to

move to more efficient operation point. This signal will de-assert at least 3.3 us

before the current consumption will exceed 20A. The minimum PSI#

assertion and de-assertion time is 1 BCLK.

RESET#

Asserting the RESET# signal resets the processor to a known state and

invalidates its internal caches without writing back any of their contents. Note

some PLL, QPI and error states are not effected by reset and only

VCCPWRGOOD forces them to a known state. For a power-on Reset, RESET#

must stay active for at least one millisecond after VCC and BCLK have reached

their proper specifications. RESET# must not be kept asserted for more than

10 ms while VCCPWRGOOD is asserted. RESET# must be held de-asserted for

at least 1 ms before it is asserted again. RESET# must be held asserted before

VCCPWRGOOD is asserted. This signal does not have on-die termination and

must be terminated on the system board. RESET# is a common clock signal.

SKTOCC#

SKTOCC# (Socket Occupied) will be pulled to ground on the processor package.

There is no connection to the processor silicon for this signal. System board

designers may use this signal to determine if the processor is present.

TCK

TCK (Test Clock) provides the clock input for the processor Test Bus (also known

as the Test Access Port).

TDI

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TESTLOW

TESTLOW must be connected to ground through a resistor for proper processor

operation.

Table 5-1.

Signal Definitions (Sheet 2 of 4)

Name

Type

Description

Notes

Содержание BX80601920 - Core i7 2.66 GHz Processor

Страница 1: ...Document 320834 004 Intel Core i7 900 Desktop Processor Extreme Edition Series and Intel Core i7 900 Desktop Processor Series Datasheet Volume 1 February 2010...

Страница 2: ...led chipset BIOS and operating system Performance will vary depending on the specific hardware and software you use For more information including details on which processors support HT Technology see...

Страница 3: ...ent Specification 23 2 11 2 VCC Overshoot Specification 29 2 11 3 Die Voltage Validation 30 3 Package Mechanical Specifications 31 3 1 Package Mechanical Drawing 31 3 2 Processor Component Keep Out Zo...

Страница 4: ...d Transient Tolerance Load Lines 25 2 4 VTT Static and Transient Tolerance Load Line 27 2 5 VCC Overshoot Example Waveform 30 3 1 Processor Package Assembly Sketch 31 3 2 Processor Package Drawing She...

Страница 5: ...gnal Group DC Specifications 28 2 15 Control Sideband Signal Group DC Specifications 29 2 16 VCC Overshoot Specifications 29 3 1 Processor Loading Specifications 34 3 2 Package Handling Guidelines 34...

Страница 6: ...6 Datasheet...

Страница 7: ...evel 3 cache Intel Advanced Digital Media Boost Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance New accelerators for improved string and text process...

Страница 8: ...Initial release November 2008 002 Added Intel Core i7 processor i7 950 Added Intel Core i7 processor Extreme Edition i7 975 June 2009 003 Added Intel Core i7 900 desktop processor i7 960 October 2009...

Страница 9: ...ore i7 900 desktop processor series will be referred to as the processor Note The Intel Core i7 900 desktop processor series refers to the Intel Core i7 900 desktop processors i7 960 i7 950 i7 940 i7...

Страница 10: ...id Array FC LGA package consisting of the processor mounted on a land grid array substrate with an integrated heat spreader IHS LGA1366 Socket The processor in the LGA 1366 package mates with the syst...

Страница 11: ...e The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any sup...

Страница 12: ...Introduction 12 Datasheet...

Страница 13: ...VCC 8 VTTA pads and 5 VSS pads associated with VTTA 28 VTTD pads and 17 VSS pads associated with VTTD 28 VDDQ pads and 17 VSS pads associated with VDDQ and 3 VCCPLL pads All VCCP VTTA VTTD VDDQ and V...

Страница 14: ...core frequency is configured during power on reset by using values stored internally during manufacturing The stored value sets the highest core multiplier at which the particular processor can opera...

Страница 15: ...VID 3 VID 2 VID 1 VID 0 VCC_MAX 0 0 0 0 0 0 0 0 OFF 0 1 0 1 1 0 1 1 1 04375 0 0 0 0 0 0 0 1 OFF 0 1 0 1 1 1 0 0 1 03750 0 0 0 0 0 0 1 0 1 60000 0 1 0 1 1 1 0 1 1 03125 0 0 0 0 0 0 1 1 1 59375 0 1 0 1...

Страница 16: ...0 1 27500 1 0 0 1 0 0 0 1 0 70625 0 0 1 1 0 1 1 1 1 26875 1 0 0 1 0 0 1 0 0 70000 0 0 1 1 1 0 0 0 1 26250 1 0 0 1 0 0 1 1 0 69375 0 0 1 1 1 0 0 1 1 25625 1 0 0 1 0 1 0 0 0 68750 0 0 1 1 1 0 1 0 1 250...

Страница 17: ...w for system testability 0 1 0 0 1 1 1 1 1 11875 1 0 1 0 1 0 1 0 0 55000 0 1 0 1 0 0 0 0 1 11250 1 0 1 0 1 0 1 1 0 54375 0 1 0 1 0 0 0 1 1 10625 1 0 1 0 1 1 0 0 0 53750 0 1 0 1 0 0 1 0 1 10000 1 0 1 0...

Страница 18: ...eference Clocks Differential DDR3 Output DDR 0 1 2 _CLK D P 3 0 DDR3 Command Signals Single ended CMOS Output DDR 0 1 2 _RAS DDR 0 1 2 _CAS DDR 0 1 2 _WE DDR 0 1 2 _MA 15 0 DDR 0 1 2 _BA 2 0 Single en...

Страница 19: ...nection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor be first in the TAP chain and followed by any other components wi...

Страница 20: ...fications shown in Table 2 5 is used with devices normally operating from a VTTD interface supply VTTD nominal levels will vary between processor families All PECI devices will operate at the VTTD lev...

Страница 21: ...ected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding t...

Страница 22: ...band and Test Access Port TAP are listed in Table 2 12 through Table 2 15 Table 2 7 through Table 2 15 list the DC specifications for the processor and are valid only while meeting specifications for...

Страница 23: ...sure external noise from the system is not coupled into the oscilloscope probe 4 Refer to Table 2 8 and Figure 2 3 for the minimum typical and maximum VCC allowed for a given current The processor sho...

Страница 24: ...5 VID 0 020 VID 0 039 VID 0 058 1 2 3 30 VID 0 024 VID 0 043 VID 0 062 1 2 3 35 VID 0 028 VID 0 047 VID 0 066 1 2 3 40 VID 0 032 VID 0 051 VID 0 070 1 2 3 45 VID 0 036 VID 0 055 VID 0 074 1 2 3 50 VID...

Страница 25: ...VID4 VID3 VID2 VID1 VID0 0 1 0 0 0 0 1 0 1 220 V 0 1 0 0 0 1 1 0 1 195 V 0 1 0 0 1 0 1 0 1 170 V 0 1 0 0 1 1 1 0 1 145 V 0 1 0 1 0 0 1 0 1 120 V 0 1 0 1 0 1 1 0 1 095 V 0 1 0 1 1 0 1 0 1 070 V 0 1 0...

Страница 26: ...5 6 VID 0 0045 VID 0 0360 VID 0 0675 7 VID 0 0105 VID 0 0420 VID 0 0735 8 VID 0 0165 VID 0 0480 VID 0 0795 9 VID 0 0225 VID 0 0540 VID 0 0855 10 VID 0 0285 VID 0 0600 VID 0 0915 11 VID 0 0345 VID 0 06...

Страница 27: ...ut High Voltage 0 57 VDDQ V 3 VOL Output Low Voltage VDDQ 2 RON RON RVTT_TERM V VOH Output High Voltage VDDQ VDDQ 2 RON RON RVTT_TERM V 4 RON DDR3 Clock Buffer On Resistance 21 31 RON DDR3 Command Buf...

Страница 28: ...ons refers to instantaneous VTTA 3 For Vin between 0 V and VTTA Measured when the driver is tristated 4 VIH and VOH may experience excursions above VTT 5 This specification applies to VCCPWRGOOD and V...

Страница 29: ...ershoot cannot exceed VID VOS_MAX VOS_MAX is the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands Tabl...

Страница 30: ...ed across the VCC_SENSE and VSS_SENSE lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limi...

Страница 31: ...ermal Interface Material TIM Processor core die Package substrate Capacitors Note 1 Socket and motherboard are included for reference and are not part of the processor package 3 1 Package Mechanical D...

Страница 32: ...Package Mechanical Specifications 32 Datasheet Figure 3 2 Processor Package Drawing Sheet 1 of 2...

Страница 33: ...Datasheet 33 Package Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 2...

Страница 34: ...ng in a direction normal to the processor IHS 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface...

Страница 35: ...ckage components and associated materials 3 8 Processor Markings Figure 3 4 shows the top side markings on the processor This diagram is to aid in the identification of the processor Table 3 3 Process...

Страница 36: ...t 3 9 Processor Land Coordinates Figure 3 5 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Processo...

Страница 37: ...CLOCK O DDR0_CLK_P 0 J19 CLOCK O DDR0_CLK_P 1 D19 CLOCK O DDR0_CLK_P 2 F18 CLOCK O DDR0_CLK_P 3 E20 CLOCK O DDR0_CS 0 G15 CMOS O DDR0_CS 1 B10 CMOS O DDR0_CS 4 B15 CMOS O DDR0_CS 5 A7 CMOS O DDR0_DQ...

Страница 38: ...6 CMOS O DDR0_MA 12 B26 CMOS O DDR0_MA 13 A10 CMOS O Table 4 1 Land Listing by Land Name Sheet 3 of 29 Land Name Land No Buffer Type Direction DDR0_MA 14 A28 CMOS O DDR0_MA 15 B29 CMOS O DDR0_MA 2 C23...

Страница 39: ...V9 CMOS I O DDR1_DQ 61 W5 CMOS I O Table 4 1 Land Listing by Land Name Sheet 5 of 29 Land Name Land No Buffer Type Direction DDR1_DQ 62 AA7 CMOS I O DDR1_DQ 63 W9 CMOS I O DDR1_DQ 7 Y39 CMOS I O DDR1...

Страница 40: ...G10 CMOS I O Table 4 1 Land Listing by Land Name Sheet 7 of 29 Land Name Land No Buffer Type Direction DDR2_DQ 38 H12 CMOS I O DDR2_DQ 39 L12 CMOS I O DDR2_DQ 4 U34 CMOS I O DDR2_DQ 40 L10 CMOS I O DD...

Страница 41: ...et 9 of 29 Land Name Land No Buffer Type Direction QPI_DRX_DN 3 AY36 QPI I QPI_DRX_DN 4 BA37 QPI I QPI_DRX_DN 5 AW38 QPI I QPI_DRX_DN 6 AY38 QPI I QPI_DRX_DN 7 AT39 QPI I QPI_DRX_DN 8 AV40 QPI I QPI_D...

Страница 42: ...37 RSVD B34 RSVD C34 RSVD G34 RSVD G33 RSVD D36 RSVD F36 RSVD E33 RSVD G36 RSVD E37 RSVD F37 RSVD E34 RSVD G35 RSVD G30 RSVD G29 RSVD H32 RSVD F33 RSVD E29 RSVD E30 RSVD J31 RSVD J30 Table 4 1 Land Li...

Страница 43: ...VD AD6 RSVD AD7 Table 4 1 Land Listing by Land Name Sheet 13 of 29 Land Name Land No Buffer Type Direction RSVD AD8 RSVD AE1 RSVD AE3 RSVD AE4 RSVD AE5 RSVD AE6 RSVD AF1 RSVD AF2 RSVD AF3 RSVD AF4 RSV...

Страница 44: ...1 Land Listing by Land Name Sheet 15 of 29 Land Name Land No Buffer Type Direction RSVD AW41 RSVD AW42 RSVD AW5 RSVD AW7 RSVD AY3 RSVD AY35 RSVD AY39 RSVD AY4 RSVD AY40 RSVD AY41 RSVD AY5 RSVD AY6 RS...

Страница 45: ...AN12 PWR VCC AN13 PWR Table 4 1 Land Listing by Land Name Sheet 17 of 29 Land Name Land No Buffer Type Direction VCC AN15 PWR VCC AN16 PWR VCC AN18 PWR VCC AN19 PWR VCC AN21 PWR VCC AN24 PWR VCC AN25...

Страница 46: ...C AV9 PWR VCC AW10 PWR Table 4 1 Land Listing by Land Name Sheet 19 of 29 Land Name Land No Buffer Type Direction VCC AW12 PWR VCC AW13 PWR VCC AW15 PWR VCC AW16 PWR VCC AW18 PWR VCC AW19 PWR VCC AW21...

Страница 47: ...e 4 1 Land Listing by Land Name Sheet 21 of 29 Land Name Land No Buffer Type Direction VDDQ F24 PWR VDDQ G17 PWR VDDQ G22 PWR VDDQ G27 PWR VDDQ H15 PWR VDDQ H20 PWR VDDQ H25 PWR VDDQ J18 PWR VDDQ J23...

Страница 48: ...6 GND VSS AL29 GND Table 4 1 Land Listing by Land Name Sheet 23 of 29 Land Name Land No Buffer Type Direction VSS AL32 GND VSS AL35 GND VSS AL36 GND VSS AL37 GND VSS AL42 GND VSS AL7 GND VSS AM11 GND...

Страница 49: ...SS AV17 GND VSS AV20 GND Table 4 1 Land Listing by Land Name Sheet 25 of 29 Land Name Land No Buffer Type Direction VSS AV22 GND VSS AV23 GND VSS AV26 GND VSS AV29 GND VSS AV32 GND VSS AV39 GND VSS AV...

Страница 50: ...S M14 GND VSS M16 GND Table 4 1 Land Listing by Land Name Sheet 27 of 29 Land Name Land No Buffer Type Direction VSS M18 GND VSS M2 GND VSS M20 GND VSS M22 GND VSS M24 GND VSS M26 GND VSS M28 GND VSS...

Страница 51: ...D AA10 PWR VTTD AA11 PWR VTTD AA33 PWR VTTD AB10 PWR VTTD AB11 PWR VTTD AB33 PWR VTTD AB34 PWR VTTD AB8 PWR VTTD AB9 PWR VTTD AC10 PWR VTTD AC11 PWR VTTD AC33 PWR VTTD AC34 PWR VTTD AC35 PWR VTTD AD34...

Страница 52: ...40 RSVD AA41 RSVD AA5 BCLK_ITP_DP CMOS O AA6 VDDPWRGOOD Asynch I AA7 DDR1_DQ 62 CMOS I O AA8 DDR_COMP 0 Analog AA9 VSS GND AB10 VTTD PWR AB11 VTTD PWR AB3 RSVD AB33 VTTD PWR AB34 VTTD PWR AB35 VTTPWRG...

Страница 53: ...GND Table 4 2 Land Listing by Land Number Sheet 3 of 29 Land No Pin Name Buffer Type Direction AF39 QPI_DTX_DP 1 QPI O AF4 RSVD AF40 QPI_DTX_DN 19 QPI O AF41 VSS GND AF42 QPI_CLKTX_DN QPI O AF43 QPI_D...

Страница 54: ...PWR AK26 VSS GND Table 4 2 Land Listing by Land Number Sheet 5 of 29 Land No Pin Name Buffer Type Direction AK27 VCC PWR AK28 VCC PWR AK29 VSS GND AK3 VSS GND AK30 VCC PWR AK31 VCC PWR AK32 VSS GND A...

Страница 55: ...VSS GND Table 4 2 Land Listing by Land Number Sheet 7 of 29 Land No Pin Name Buffer Type Direction AM36 RSVD AM37 VSS GND AM38 RSVD AM39 VSS GND AM4 RSVD AM40 QPI_DRX_DN 15 QPI I AM41 QPI_DRX_DN 16 Q...

Страница 56: ...PI I AP43 VSS GND AP5 VSS GND Table 4 2 Land Listing by Land Number Sheet 9 of 29 Land No Pin Name Buffer Type Direction AP6 VSS GND AP7 PSI CMOS O AP8 VID 6 CMOS O AP9 VID 5 CSC 2 CMOS I O AR1 RSVD A...

Страница 57: ...PWR AU14 VSS GND Table 4 2 Land Listing by Land Number Sheet 11 of 29 Land No Pin Name Buffer Type Direction AU15 VCC PWR AU16 VCC PWR AU17 VSS GND AU18 VCC PWR AU19 VCC PWR AU2 RSVD AU20 VSS GND AU2...

Страница 58: ...WR AW22 VSS GND AW23 VSS GND Table 4 2 Land Listing by Land Number Sheet 13 of 29 Land No Pin Name Buffer Type Direction AW24 VCC PWR AW25 VCC PWR AW26 VSS GND AW27 VCC PWR AW28 VCC PWR AW29 VSS GND A...

Страница 59: ...WR B33 RSVD B34 RSVD B35 RSVD B36 RSVD Table 4 2 Land Listing by Land Number Sheet 15 of 29 Land No Pin Name Buffer Type Direction B37 VSS GND B38 DDR0_DQ 31 CMOS I O B39 DDR0_DQS_P 3 CMOS I O B4 BPM...

Страница 60: ...O D18 VDDQ PWR D19 DDR0_CLK_P 1 CLOCK O Table 4 2 Land Listing by Land Number Sheet 17 of 29 Land No Pin Name Buffer Type Direction D2 BPM 6 GTL I O D20 RSVD D21 DDR1_CLK_N 0 CLOCK O D22 DDR1_MA 7 CM...

Страница 61: ...VD F26 DDR1_MA 15 CMOS O F27 RSVD F28 RSVD Table 4 2 Land Listing by Land Number Sheet 19 of 29 Land No Pin Name Buffer Type Direction F29 VSS GND F3 DDR0_DQ 38 CMOS I O F30 RSVD F31 RSVD F32 RSVD F33...

Страница 62: ...37 DDR2_DQ 27 CMOS I O Table 4 2 Land Listing by Land Number Sheet 21 of 29 Land No Pin Name Buffer Type Direction H38 RSVD H39 DDR2_DQ 28 CMOS I O H4 DDR1_DQ 43 CMOS I O H40 VSS GND H41 DDR0_DQ 16 CM...

Страница 63: ...sting by Land Number Sheet 23 of 29 Land No Pin Name Buffer Type Direction K8 RSVD K9 RSVD L1 DDR0_DQ 42 CMOS I O L10 DDR2_DQ 40 CMOS I O L11 DDR2_DQ 44 CMOS I O L12 DDR2_DQ 39 CMOS I O L13 DDR2_DQ 35...

Страница 64: ...n Name Buffer Type Direction N36 DDR2_DQ 21 CMOS I O N37 DDR1_DQ 14 CMOS I O N38 DDR1_DQ 15 CMOS I O N39 DDR1_DQ 11 CMOS I O N4 RSVD N40 VSS GND N41 DDR0_DQ 8 CMOS I O N42 RSVD N43 DDR0_DQ 9 CMOS I O...

Страница 65: ...R0_DQ 6 CMOS I O U42 VSS GND Table 4 2 Land Listing by Land Number Sheet 27 of 29 Land No Pin Name Buffer Type Direction U43 DDR0_DQS_N 0 CMOS I O U5 DDR2_DQ 56 CMOS I O U6 DDR2_DQ 57 CMOS I O U7 VSS...

Страница 66: ...GND Y34 DDR1_DQ 3 CMOS I O Y35 DDR1_DQ 2 CMOS I O Y36 VSS GND Y37 DDR1_DQS_N 0 CMOS I O Y38 DDR1_DQS_P 0 CMOS I O Y39 DDR1_DQ 7 CMOS I O Y4 RSVD Y40 DDR1_DQ 6 CMOS I O Y41 VSS GND Y5 RSVD Y6 VSS GND Y...

Страница 67: ...stor QPI_DRX_DN 19 0 QPI_DRX_DP 19 0 I I QPI_DRX_DN 19 0 and QPI_DRX_DP 19 0 comprise the differential receive data for the QPI port The inbound 20 lanes are connected to another component s outbound...

Страница 68: ...s an indication that the VR controller does not currently need to be able to provide ICC above 20A and the VR controller can use this information to move to more efficient operation point This signal...

Страница 69: ...e a subsequent rising edge of VCCPWRGOOD In addition at the time VCCPWRGOOD is asserted RESET must be active The PWRGOOD signal must be supplied to the processor It should be driven high throughout bo...

Страница 70: ...input signal to be a clean indication that the VTT power supply is stable and within specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches f...

Страница 71: ...to the processor case temperature thermal profile at the customer defined boundary conditions is expected to be compliant with this update No redesign of the thermal solution should be necessary A fan...

Страница 72: ...Section 1 2 for details on system thermal solution design thermal profiles and environmental considerations Notes 1 These values are specified at VCC_MAX for all processor frequencies Systems must be...

Страница 73: ...e in C y 43 2 0 19 P Table 6 2 Processor Thermal Profile Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C Power W TCASE_MAX C 0 43 2 34 49 7 68 56 1 100 62 2 2 43 6 36 50 0 70 56 5 102 62 6...

Страница 74: ...ines see Section 1 2 for details on characterizing the fan speed to CA and ambient temperature measurement Notes 1 The ambient temperature is measured at the inlet to the processor thermal solution 2...

Страница 75: ...hodology and attaching the thermocouple refer to the appropriate processor Thermal and Mechanical Design Guidelines see Section 1 2 Notes 1 Figure is not to scale and is for reference only 2 B1 Max 45...

Страница 76: ...intelligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method as with previous generation processors supporting TM1 or TM2 The temperatur...

Страница 77: ...l 0 and PROCHOT is still active then a second frequency and voltage transition will take place This sequence of temperature checking and Frequency VID reduction will continue until either the minimum...

Страница 78: ...temperature TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio VID state 6 2 2 4 Critical Temperature Flag If TM2 is unable to reduce the processor temperature th...

Страница 79: ...ally shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 5 1 THERMTRIP activation is independent of processor activity The temperature at which TH...

Страница 80: ...econds over which the DTS temperature values are averaged Short averaging times will make the averaged temperature values respond more quickly to DTS changes Long averaging times will result in better...

Страница 81: ...ime frame when reliable data is not available using PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to...

Страница 82: ...ABSOLUTE STORAGE applies to unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 Intel branded board products are certified to meet the following te...

Страница 83: ...ivalent MWAIT C state requests inside the processor and do not directly result in I O reads to the system The P_LVLx I O Monitor address does not need to be set up before using the P_LVLx I O read int...

Страница 84: ...he MWAIT instruction RESET will cause the processor to initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the C1 state See the Intel 64 and IA...

Страница 85: ...cessor depending on the core power states and permission from the rest of the system as described in the following sections 7 2 2 1 Package C0 State This is the normal operating state for the processo...

Страница 86: ...by the processor in response PM Request PMReq messages from the chipset The processor itself will never request a particular S state Notes 1 If the chipset requests an S state transition which is not...

Страница 87: ...steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the VCC is ch...

Страница 88: ...Features 88 Datasheet...

Страница 89: ...er are dimensioned in millimeters and inches in brackets Figure 8 1 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel bo...

Страница 90: ...tsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 8 2 Side View and Figure 8 3...

Страница 91: ...1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation Figure 8 3 Space Requirements for the Boxed Processor top view Figure 8 4 Space R...

Страница 92: ...ch is an open collector output that pulses at a rate of 2 pulses per fan revolution A baseboard pull up resistor provides VOH to match the system board mounted fan speed monitor requirements if applic...

Страница 93: ...the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink red...

Страница 94: ...oxed Processor Specifications 94 Datasheet Figure 8 7 Boxed Processor Fan Heatsink Airspace Keepout Requirements top view Figure 8 8 Boxed Processor Fan Heatsink Airspace Keepout Requirements side vie...

Страница 95: ...ssis temperature should be kept below 40 C Meeting the processor temperature specification see Chapter 6 is the responsibility of the system integrator The motherboard must supply a constant 12 V to t...

Страница 96: ...accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out...

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