Errata
Specification Update
21
BH17
Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
Problem:
In certain circumstances, when a floating point exception (#MF) is pending during
single-step execution, processing of the single-step debug exception (#DB) may be
mishandled.
Implication:
When this erratum occurs, #DB is incorrectly handled as follows:
•
#DB is signaled before the pending higher priority #MF (Interrupt 16)
•
#DB is generated twice on the same instruction
Workaround:
None.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH18
Unsynchronized Cross-Modifying Code Operations Can Cause
Unexpected Instruction Execution Results
Problem:
The act of one processor, or system bus master, writing data into a currently
executing code segment of a second processor with the intent of having the second
processor execute that data as code is called cross-modifying code (XMC). XMC that
does not force the second processor to execute a synchronizing instruction, prior to
execution of the new code, is called unsynchronized XMC. Software using
unsynchronized XMC to modify the instruction byte stream of a processor can see
unexpected or unpredictable execution behavior from the processor that is executing
the modified code.
Implication:
In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel Architecture
Software Developer's Manual Volume 3A: System Programming Guide, including a
General Protection Fault (#GP) or other unexpected behaviors.
Workaround:
In order to avoid this erratum, programmers should use the XMC synchronization
algorithm as detailed in the Intel Architecture Software Developer's Manual Volume
3A: System Programming Guide, Section: Handling Self- and Cross-Modifying Code.
Status:
For the steppings affected, see the Summary Tables of Changes.
BH19
A Page Fault May Not be Generated When the PS bit is set to “1” in a
PML4E or PDPTE
Problem:
On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is
reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory
access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur.
Due to this erratum, PS of such an entry is ignored and no page fault will occur due to
its being set.
Implication:
Software may not operate properly if it relies on the processor to deliver page faults
when reserved bits are set in paging-structure entries.
Workaround:
Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit 0) set to
“1”.
Status:
For the steppings affected, see the Summary Tables of Changes.
