set flash_out_min_dly [expr $flash_data_tracemin - $flash_Th - $flash_clk_tracemax]
set_output_delay -add_delay -max \
-clock [get_clocks {FLASH_CLK}] $flash_out_max_dly [get_ports {flash_dc1_io1 flash_dc1_io3 flash_dc1_io4
flash_dc1_io5 flash_dc1_io2}]
set_output_delay -add_delay -min \
-clock [get_clocks {FLASH_CLK}] $flash_out_min_dly [get_ports { flash_dc1_io1 flash_dc1_io3 flash_dc1_io4
flash_dc1_io5 flash_dc1_io2}]
Example 6. Set input delay for input pins
Example below sets the input delay for the QSPI flash data.
set flash_tco_max 7.000
set flash_tco_min 1.000
set in_max_dly [expr $flash_data_tr $flash_t $flash_clk_tracemax]
set in_min_dly [expr $flash_data_tr $flash_t $flash_clk_tracemin]
set_input_delay -clock { FLASH_CLK } -max $in_max_dly [get_ports {flash_dc1_io1 flash_dc1_io3 flash_dc1_io4
flash_dc1_io5}]
set_input_delay -clock { FLASH_CLK } -min $in_min_dly [get_ports {flash_dc1_io1 flash_dc1_io3 flash_dc1_io4
flash_dc1_io5}]
3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash
Example 7. Create a
FLASH_CLK
clock
Example below assigns CFI flash clock pin (
flash_clk
) to the flash clock. You constrain the flash_clk pin only when using
burst mode.
create_generated_clock -name FLASH_CLK -source [get_ports {clk_50m_max5}] [get_ports {flash_clk}]
Example 8. Set output delay for output pins
Example below sets the output delay for CFI flash output pins.
set flash_data_tracemax 0.250
set flash_data_tracemin 0.000
set flash_clk_tracemax 0.250
set flash_clk_tracemin 0.000
set flash_Tsu 3.500
set flash_Th 2.000
set flash_out_max_dly [expr $flash_data_tr $flash_Tsu - $flash_clk_tracemin]
set flash_out_min_dly [expr $flash_data_tracemin - $flash_Th - $flash_clk_tracemax]
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
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