Intel 845 CHIPSET PLATFORM FOR SDR - DESIGN GUIDE UPDATE 2004 Скачать руководство пользователя страница 7 | Manualshive

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General Design Considerations

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General Design Considerations

There are no General Design Considerations in this Design Guide Update revision.

Design Guide Update

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Содержание 845 CHIPSET PLATFORM FOR SDR - DESIGN GUIDE UPDATE 2004

Страница 1: ...Design Guide Update March 2004 Notice The Intel 845 chipset family may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are documented in the Specification Update Document Number 250425 003 ...

Страница 2: ...nce or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel 845 chipset family may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current...

Страница 3: ...Preface R Contents Preface 5 Nomenclature 5 Codes Used in Summary Table 6 General Design Considerations 7 Schematic Layout and Routing Updates 9 Documentation Changes 11 Design Guide Update 3 ...

Страница 4: ...ns 3 Added Documentation Change 5 Change Table 3 System Bus Routing Summary for the Processor 4 Added Documentation Change 6 Add Section 13 2 Intel Boxed Processor Mechanical Keep Outs 5 Added Documentation Change 7 Add Section 15 1 3 Intel Boxed Processor Mechanical Keep Outs 6 Added Schematic Layout and Routing Updates 1 Schematic change to the 82845 MCH HSWING Circuit May 2002 003 1 Added Docum...

Страница 5: ...on of this document are consolidated into the public design guide update document when the public design guide document is first published This design guide update document contains a complete list of all known information types Affected Documents Document Title Document Number Intel Pentium 4 Processor in 478 pin Package and Intel 845 Chipset Platform for SDR Design Guide January 2002 298354 002 ...

Страница 6: ...it NO Plans DOCUMENTATION CHANGES 1 Doc Change Section 12 4 2 3 3V V5REF Sequencing 2 Doc Change Section 14 8 Power and Ground V5REF_SUS 3 Doc Replace Figure 118 Intel 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map 4 Doc Add Section 4 6 7 Electrostatic Discharge Platform Recommendations 5 Doc Change Table 3 System Bus Routing Summary for the Processor 6 Doc Add Section 13 ...

Страница 7: ...General Design Considerations R General Design Considerations There are no General Design Considerations in this Design Guide Update revision Design Guide Update 7 ...

Страница 8: ...General Design Considerations R This page is intentionally left blank 8 Design Guide Update ...

Страница 9: ... Sheet 11 of the Intel 845 SDR Schematics Rev 1 3 contains a circuit at grid location C 7 This circuit has a VCCP input and an HSWING output Capacitor C5D6 is shown as a series capacitor between VCCP and the HSWING output This circuit is not correct as shown Capacitor C5D6 is a decoupling capacitor It should connect the HSWING output of this circuit to GND so that resistor R5D5 and capacitor C5D6 ...

Страница 10: ...Schematic Layout and Routing Updates R This page is intentionally left blank 10 Design Guide Update ...

Страница 11: ...ected to either VccSus3_3 or 5V_Always 5V_AUX rails 2 Changed Change Section 14 8 Power and Ground V5REF_SUS Change the second bullet in the description of V5REF_SUS to read V5REF_SUS only affects 5 V tolerance for USB OC 3 0 pins and can be connected to either VccSUS3_3 or 5V_Always 5V_AUX if 5V tolerance on these OC 3 0 is not needed If 5V tolerance on OC 3 0 is needed then V5REF_SUS USB must be...

Страница 12: ...new material is added as Section 4 6 7 Electrostatic Discharge Platform Recommendations 4 6 7 Electrostatic Discharge Platform Recommendations Electrostatic discharge ESD into a system can lead to system instability and possibly cause functional failures when a system is in use There are system level design methodologies that when followed can lead to higher ESD immunity Electromagnetic fields due...

Страница 13: ...be connected to two chassis mounting holes as seen in Figure 2 This will allow ESD current to travel to the chassis instead of the board Ground stitching vias should be placed throughout the entire ground fill if possible It is important that the vias are placed along the board edge Ground stitching vias for the ground fill should be 100 150 mils apart or less In conclusion Intel recommends the fo...

Страница 14: ...ocessor in Section 4 1 The parameter Clock keep out zones is changed as shown Clock keep out zones Refer to Table 55 BCLK 1 0 Routing Guidelines of this Design Guide 6 Add Section 13 2 Intel Boxed Processor Mechanical Keep Outs The following new section is added 13 2 Intel Boxed Processor Mechanical Keep Outs Verify Intel s Boxed Processor mechanical keep outs are marked and visible during board l...

Страница 15: ...rocessor mechanical keep outs are marked and visible during board layout This keep out zone should be considered during chassis selection 8 Revise Section 14 1 Schematic Checklist Host Interface PWRGOOD Revise Section 14 1 Schematic Checklist Host Interface PWRGOOD with the following Signal Description Processor Intel ICH2 Signals PWRGOOD Connects to ICH2 CPUPWRGD pin Note that a weak pullup to V_...

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