Documentation Changes
R
Figure 3, Bottom signal layer before the ground fill near the I/O area
Ground Fill
Figure 4, Bottom signal layer after the ground fill near the I/O area
5.
Change Table 3, System Bus Routing Summary for the Processor
Reference Table 3, System Bus Routing Summary for the Processor, in Section 4.1. The
parameter “Clock keep out zones” is changed as shown:
Clock keep out zones Refer to Table 55, BCLK [1:0]# Routing Guidelines, of this
Design Guide.
6.
Add Section 13.2, Intel® Boxed Processor Mechanical Keep-Outs
The following new section is added:
13.2
Intel® Boxed Processor Mechanical Keep-Outs
Verify Intel’s Boxed Processor mechanical keep-outs are marked and visible during board layout.
This keep-out zone should be considered during chassis selection.
14
Design Guide Update
