92
Memory Controller
7.4.3.2
DDR 333 Embedded Clock Routing Recommendations
This section lists the recommendations for the DDR 333 clock signals. Refer to
for
buffered clock topology,
for unbuffered clock topology. Refer to
for a summary
of DDR 333 embedded clock routing guidelines. Refer to
for a description of the segment
lengths and matching requirements for buffered clock topology. Refer to
for a description
of unbuffered clock topology information.
Figure 45.
Embedded DDR 333 Buffered Clock Topology
PLL
Feedback
SDRAM
OUT
FB_IN
TL0_reg
TL0_sdram
TL1_sdram
TL
2_
sd
ram
TL2
_sd
ram
120 ohms
+/- 5%
TL1
T
L
2
TL0
TL0_PLLFB
TL3_PLLFB
TL2_PLLFB
Register
Register
Rp 240 ohms
TL
1_
reg
TL1
_re
g
TL2_reg
TL2_reg
120 ohms
+/- 5%
120 ohms
+/- 5%
Rp 240 ohms
+/- 5%
+/- 5%
Содержание 80331
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