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Development Kit Features

Generation Intel

Core™ Processor with Intel

6 Series Chipset Development Kit

User Guide

March 2011

Document Number: 325208-001

Strap

CFG4

An eDP panel device is

connected to eDP port (Short

J1E1 – (1-2))

No Display Port connected to eDP

(default—J1E1- (1-X))

3.1.5.2

External Graphics Support

The development board supports external graphics through an on-board PCIe graphics

x16 slot. This interface is fully compliant to the PCIe Base Specification Revision 2.0.

The board supports Gen 2 (5.0 GT/s) PCIe frequencies.

Switchable Graphics is also supported on the board. It can be validated using the Elk

Creek add-in card.

Table 6. CFG[6] and [5] Straps Combined and Used for PEG Interface Configuration

Strap

CFG[6:5]

X16 PEG interface (Default-

UNSTUFF R2R31, R2R25)

PEG 2x8 bifurcation enabled

(STUFF R2R31)

Table 7. Other PEG Interface Straps

Strap

CFG2

Lane-reversed (STUFF R2R47)

Not lane-reversed. (Default)

CFG7

PEG wait for BIOS for training

(STUFF R2R20)

PEG training followed by RST#

deassertion (Default -

UNSTUFF R2R0)

NOTE: The processor supports lane-reversal of the PEG lanes, but the development board uses

non-lane-reversed routing.

3.1.5.3

Direct Media Interface (DMI)-2 Interface

The development board supports x4 DMI-2 bidirectional lanes (four lanes in each

direction) between the processor and PCH. DMI is the key interface between the

processor and the Intel

6 Series Chipset. Apart from this, it is also used to transfer

information such as ME data, and power-management signals such as SLP#,

DPRSLP#, DPRSLPVR#, STP_CLK#. All the power-management handshakes happen

across this interface. The board supports a maximum speed of 5 GT/s (Gen 2 speed).

The series resistors in the path of FDI/DMI lanes for earlier platforms are removed in

the development board.

3.1.6

Intel

Flexible Display Interface (Intel

FDI)

Intel FDI is a dedicated link to transmit the display-related pixel information over

unidirectional 2x4 lanes from processor to PCH. The maximum supported speed for

Содержание 6 SERIES

Страница 1: ...Document Number 325208 2nd Generation Intel Core Processor Family with Intel 6 Series Chipset Development Kit User Guide March 2011...

Страница 2: ...reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Intel processor numbers are not a measure of pe...

Страница 3: ...8 1 Configuring the BIOS 20 2 8 2 Programming BIOS Using a Bootable USB Device 20 3 Development Kit Features 22 3 1 Processor Support 24 3 1 1 Clock Requirements 25 3 1 2 Processor Voltage Regulator...

Страница 4: ...Back Panel Connectors 51 4 3 Configuration Settings 52 4 3 1 Configuration Jumpers Switches 52 4 4 Power On and Reset Button 53 4 5 LEDs 54 5 Quick Start 56 5 1 Required Peripherals 56 5 2 Instruction...

Страница 5: ...erent Port Mappings 32 Table 10 Selection of I O Voltage for the Intel High Definition Audio 33 Table 11 SATA Ports 34 Table 12 USB Port Mapping 39 Table 13 USB2 0 Ports 40 Table 14 Jumper Settings fo...

Страница 6: ...on Intel Core Processor with Intel 6 Series Chipset Development Kit User Guide March 2011 6 Document Number 325208 001 Revision History Document Number Revision Number Description Revision Date 325208...

Страница 7: ...ent The last few sections explain how to obtain literature and contact customer support Getting Started describes the contents of the development kit and explains the basics steps necessary to get the...

Страница 8: ...pF W V A F s W The following abbreviations are used to represent units of measure amps amperes gigabytes gigabits giga transfers kilobytes kilo ohms milliamps mill amperes megabytes megahertz millisec...

Страница 9: ...rposer card that provides Express card support for the development board Flight Time Flight time is a term in the timing equation that includes the signal propagation delay any effects the system has...

Страница 10: ...ctor die to the package substrate A pad is only observable in simulations Pin The contact point of a component package to the traces on a substrate such as the motherboard Signal quality and timings m...

Страница 11: ...stalk signal from another network is called the victim network Table 3 defines acronyms used throughout this document Table 3 Acronyms Acronym Definition AC Audio Codec ACPI Advanced Configuration and...

Страница 12: ...Access EMI Electro Magnetic Interference eSATA External Serial Advanced Technology Attachment ESD Electrostatic Discharge EV Engineering Validation EVMC Electrical Validation Margining Card ERB Early...

Страница 13: ...LAN Local Area Network LED Light Emitting Diode LOM LAN on Motherboard LPC Low Pin Count often used in reference to LPC bus LS Low speed Refers to USB LVDS Low Voltage Differential Signaling MC Modem...

Страница 14: ...e Detect SPI Serial Peripheral Interface SPWG Standard Panels Working Group http www spwg org SSO Simultaneous Switching Output SUT System Under Test STR Suspend To RAM TCO Total Cost of Ownership TCP...

Страница 15: ...Cad Symbol Files 431414 Huron River Platform Power Sequence Product Specification 437432 Huron River Platform Design Guide 436735 2nd Generation Intel Core Processor Family Mobile External Design Spec...

Страница 16: ...ement Technology Intel AMT software installation kit Development Kit User Guide this document Pre assembled development system which includes o Development board o Chassis and mounting screws installe...

Страница 17: ...the board The network interface will not be operational until after all the necessary drivers have been installed A standard PCI PCI Express adapter may be used in conjunction with or in place of the...

Страница 18: ...t board is susceptible to ESD damage and such damage may cause product failure or unpredictable operation 2 5 System Setup Please complete the steps outlined below to ensure the successful setup and o...

Страница 19: ...fault and can be enabled in setup 4 The PCIe hot plug support has to be enabled in setup if hot plug detect is required 5 Save and exit the BIOS setup The system boots and is ready for use Note Fan he...

Страница 20: ...ROM Follow these steps to program the system BIOS using a bootable USB device 1 Prepare the workspace as outlined in Section 2 4 2 Set up the system as outlined in Section 2 5 3 Unplug the hard disk...

Страница 21: ...the PWR button on the board The board will not power on but a couple of LEDs will flash 15 Switch the power supply off to power down the board a Remove the CMOS CLR jumper J5F3 16 Unplug the bootable...

Страница 22: ...ocessor supported in 989 pin rPGA package in Socket G Supports two DDR channels The development board supports x4 in each direction Direct Media Interface DMI two interfaces working at 5 GT s the boar...

Страница 23: ...t add in card Port C Switchable connection to x16 connector at J8C2 or docking connector at J9C1 Port D Unpopulated stuffing option connection to HDMI connector at J3A1 Video DMC Display Mini PCIe con...

Страница 24: ...s SMC_WAKE_SCI LPC 1x LPC slot Includes sideband headers SMC KBC H8S 2117 microcontroller two PS 2 ports one scan matrix keyboard connector ACPI compliant Clocks CK505 system clock Board supports both...

Страница 25: ...A CLK and ALERT for regulating both the processor core and graphics core voltages Some of the main differences in the platform with the introduction of SVID are SVID can be used to communicate the pow...

Страница 26: ...t The development board supports dual channel DDR3 memory interface with one SODIMM per channel The integrated memory controller can support a maximum of two ranks of memory per channel There are two...

Страница 27: ...e processor has dedicated eDP ports and an on board eDP connector is provided to support this feature The Eaglemont AIC is not required to support eDP from the processor To enable eDP J8D3 should be 1...

Страница 28: ...TUFF R2R47 Not lane reversed Default CFG7 PEG wait for BIOS for training STUFF R2R20 PEG training followed by RST deassertion Default UNSTUFF R2R0 NOTE The processor supports lane reversal of the PEG...

Страница 29: ...t silicon damage may occur 3 1 8 Processor Active Cooling The development board supports PWM based fan speed control Fan circuitry is controlled by the signal CPU_PWM_FAN signal from the EC On the boa...

Страница 30: ...e ports By default four of those IO ports have been routed to x1 connectors one to a x4 connector one to LAN one to Display Mini PCIe connector and one to docking Slot 1 and 2 are in line and close to...

Страница 31: ...evelopment Kit Features 2nd Generation Intel Core Processor with Intel 6 Series Chipset Development Kit March 2011 User Guide Document Number 325208 001 31 Figure 3 PCIe Port Mapping Schematic Snapsho...

Страница 32: ...ed Xd Rd Xc Rc DMC not supported 7 Xb Ra Xa Rb Docking x1 not supported Slot 6 Xh Slot 5 as x1 supported Xf Xg Xe Re LAN supported Xc Rc Rd Xd DMC supported 7 8 Xb Rb Xa Ra Docking x2 supported Dockin...

Страница 33: ...ard is required to enable the Intel HD Audio functionality The development board supports low voltage LV high definition codecs I O R8E1 R8R11 and R8R12 R8R10 resistors are used to select between 3 3...

Страница 34: ...nect default eSATA optional J9C1 Docking connector The development board has a power connector J8J1 to power the serial ATA hard disk drive for direct connect For cable connect SATA the power connecto...

Страница 35: ...se dual USB connector and the bottom port used for the DP connector Display Port connectors are also available on the Eaglemont 2 Fab 3 AIC Figure 5 Back Panel Connectors Embedded Display Port eDP Por...

Страница 36: ...HDMI Support One DP and one HDMI connector are provided on the development board Port D of the Digital Display Interface on the PCH is mapped to on board DP HDMI and DMC connectors DP is the default...

Страница 37: ...h 0 Ohm An option is provided for USB2 0 port 0 to be connected to DMC For this the following reworks have to be done STUFF R5B12 R5B13 R6A11 R6A12 with 0 Ohms UNSTUFF R5B11 R5B14 Figure 7 Mini PCIe C...

Страница 38: ...rd can support switchable graphics with eDP from the PCH as display Figure 8 Switchable Graphics with eDP from PCH eDP over Port D Use the following step 1 Connect a cable from on board DP J5A1 connec...

Страница 39: ...rt 0 Back Panel I O Connector J5A1 stacked dual USB and DP connector Port 1 Back Panel I O Connector J5A1 stacked dual USB and DP connector Port 2 Back Panel I O Connector J3A2 stacked dual USB2 0 con...

Страница 40: ...FIR Fast IR and CIR Consumer IR The option to select between these is supported through software and GPIO pin IR_MODE on the SIO 3 2 11 System Management Controller SMC Keyboard Controller KBC A Rene...

Страница 41: ...he footprints are positioned over one another By default U8C2 and U8D2 are stuffed SPI sockets can be used Socket KOZ is available and a Dedi Prog Header J8E1 has been provided for SPI programming Tab...

Страница 42: ...e BCLK frequency can be set by stuffing unstuffing the resistor pairs R6F25 and R6F26 R6F27 and R6F22 and R6G1 and setting the jumper J6G1 For the board the default clock frequency must be 100 MHz and...

Страница 43: ...ion Intel Core processor family and Intel 6 Series Chipset platform 3 2 12 3 CPU_ITP Clock and XDP Clock The clock configuration for the clock to XDP and the clock for top side probing GDXC connected...

Страница 44: ...R6W4 2 R6W2 R6W5 ITP 3 R6W3 R6W6 Option for resistor between R6W2 1 and R6W3 2 Reworks required for FCIM support related to ITP and XDP clock Post Power On boards STUFF UNSTUFF XDP default 2 R6W2 R6W...

Страница 45: ...DC switching power supply or Mobile Brick or up to two external batteries The board contains all of the voltage regulators necessary to power up the system There are two main supported power supply co...

Страница 46: ...es include Sparkle Model No FSP300 60BTVS meets this requirement and is an ATX12V 1 1 specification compliant The following 20 pin ATX power supplies may also work if you can t acquire the above model...

Страница 47: ...16 lists the power management states that have been defined for the development board The board Controller Link CL operates at various power levels called M states Table 16 Development Board Power Ma...

Страница 48: ...t Development Kit User Guide March 2011 48 Document Number 325208 001 4 Development Board Summary 4 1 Features The following figures show the major components of the development board and Table 17 giv...

Страница 49: ...D2 5 PCIe slot5 J6C1 6a PCIe slot1 J6C2 6b PCIe slot2 J6D2 7 PEG slot J5C1 8 CPU U3E1 9 IMVP VR EU1B1 10 CPU XDP J1C1 11 Power on switch SW1E1 12 Reset switch SW1E2 13 Power Jack J1F2 14a Battery B J1...

Страница 50: ...de March 2011 50 Document Number 325208 001 Figure 13 Development Board Components Bottom View Table 18 Development Board Components List Bottom View Item Description Ref Des 1 LAN PHY EU7M1 2 Display...

Страница 51: ...rent protected Do not use these connectors for powering devices external to the computer chassis A fault in the load presented by the external devices could cause damage to the computer the interconne...

Страница 52: ...DR3 THERMAL SENSOR 10 J1E1 1 X DISPLAY PORT PRESENCE 12 J1J1 2 3 PM_EXTTS CONTROLLER 13 J5F2 1 X SRTC RST 19 J5F3 1 X RTC RST 19 J9F4 1 2 RST SEL FOR PCIe Graphics 17 J8D3 2 3 LVDS EDP VDD EN 18 J8D2...

Страница 53: ...3 SA VR 61 J1B2 1 X IMVP7 VR ENABLE 64 J5G3 1 X G3 SUPPORT 70 J1E4 1 X FORCE POWER UP VBAT 70 J1F1 1 X FORCE SHUT DOWN 70 A jumper consists of two or more pins mounted on the motherboard When a jumper...

Страница 54: ...s 1 LID SWITCH SW9H2 1 2 2 VIRTUAL DOCKING SW9H1 1 2 3 VIRTUAL BATTERY SW9H3 1 2 4 5 LEDs The following LEDs provide status of various functions Table 23 Development Board LEDs Function Reference Desi...

Страница 55: ...ary 2nd Generation Intel Core Processor with Intel 6 Series Chipset Development Kit March 2011 User Guide Document Number 325208 001 55 Function Reference Designator Page on the Schematics for referen...

Страница 56: ...1 1 Remove all the power supplies to the board 2 Connect the Dedi Prog SF100 at J8E1 3 Set jumpers J8C4 and J8C5 at 1 2 4 Set jumper J8D1 at 1 2 for SPI 0 and flash the bin image corresponding to SPI...

Страница 57: ...y where you extracted the files run the following command line KSCFLAxx ksc bin Remote where xx refers KSC flash utility version number 7 This file will program ksc bin to the KSC flash memory through...

Страница 58: ...The jumper pins that need to be shorted by default are Table 25 Key Jumpers Reference Designator Description Default Setting 10 J4B1 ON BOARD DDR3 THERMAL SENSOR 1 2 11 J4B3 ON BOARD DDR3 THERMAL SENS...

Страница 59: ...CKT H8 PROGRAMMING 1 2 20 J8C7 IN CKT H8 PROGRAMMING 1 2 21 J8G5 H8 MODE SELECTION 1 2 22 J9H1 VAUX SELECT 1 2 23 J6G2 VCCP VR VOLTAGE SELECT 1 2 24 J9G1 BOOT BLOCK PROGRAMING 1 2 25 J5C5 SA VR 2 3 26...

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