DTR-4.6
IC BLOCK DIAGRAMS AND DESCRIPTIONS
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y
-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q7
A0~A18
WE
OE
CE
BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
PIN NAME
A0~A18
Address Input
Q0~Q7
Data Input/Output
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
VCC
Power Supply Pin (+5V)
GND
Ground Pin
MX26LV040-70/EN29LV040A(4M-bit CMOS High Speed Flash Memory)
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A15
A12
A7
A6
A5
A4
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
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