Ingenic XBurst 2 CPU Core, Руководство по программированию

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CP0
3.3.2.3 EntryLo0, EntryLo1 Register (CP0 Register 2, 3, Select 0)
The pair of EntryLo registers acts as the interface between the TLB and the TLBR, TLBWI, and
TLBWR instructions. The contents of the EntryLo0 and EntryLo1 registers are undefined after an
address error, TLB invalid, TLB modified, or TLB refill exceptions.
EntryLo0, EntryLo1 Register
31 30 29 26 25 6 5 3 2 1 0
RI XI 0 PFN C D V G
Name Bits Description R/W Reset
RI 31 Read Inhibit. If this bit is set, an attempt to read data from
the page will trigger a TLB Invalid exception, even if the
V( Valid) bit is set.
R/W 0
XI 30 Execute Inhibit. If this bit is set, an attempt to fetch from the
page will trigger a TLB Invalid exception, even if the V
(Valid) bit is set.
R/W 0
0 29:26 Must be written as zero; returns zero on read R 0
PFN 25:6 Page Frame Number. The PFN field corresponds to bits
31..12 of the physical address.
R/W 0
C 5:3 Cache attribute of the page.
See Table 6-2 Cache Coherency Attributes for detail.
R/W 0
D 2 Dirty attribute of the page. The "Dirty" flag indicates that the
page has been written, and/or is writable. If D has been set,
stores to the page are permitted. However, if D has been
cleared, stores to the page cause a TLB Modified exception.
R/W 0
V 1 Valid attribute of the page. If this bit is a zero, accesses to
the page cause a TLB Invalid exception.
This bit can make just one of a pair of pages be valid
R/W 0
G 0 Global attribute of the page. The "Global" bit. On a TLB
entry update, the logical AND result of the G bits in both the
EntryLo0 and EntryLo1 registers becomes the G bit to be
filled in Entry0/Entry1 TLB entry. If the TLB entry G bit is a
one, then the ASID comparisons are ignored during TLB
matches.
R/W 0
XBurst®2
CPU Core Programming Manual
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