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Application Note

29 of 33

002-33887 Rev. *A

2022-05-25

Using the Watchdog Timer in XMC7000 family MCUs

Definitions, acronyms, and abbreviations

Table 6

Definitions, acronyms, and abbreviations

Terms

Definitions

AHB

Advanced High-performance Bus

CPU

Central Processing Unit

CPUSS

CPU subsystem

ECO

High-frequency crystal oscillator

ILO0

32-kHz internal low-speed oscillator

IRQ

Interrupt request

ISR

Interrupt Service Routine

kHz

kilohertz

LFCLK

Low-frequency clock

MCWDT

Multi-Counter Watchdog Timer

ms, msec

milliseconds

POR

Power-on reset

PPU

Peripheral Protection Unit

sec

second

Software

DDD

External high-voltage supply

WCO

Low-frequency watch crystal oscillator

WDT

Watchdog Timer

WIC

Wakeup interrupt controller

Содержание XMC7200

Страница 1: ...s Table of contents About this document 1 Table of contents 1 1 Introduction 3 2 Basic WDT 4 2 1 Source clock 5 2 2 WDT timer counter 5 2 3 Register protection 5 2 4 Warning interrupt 5 2 5 Timeout mode 6 2 6 Window mode 7 2 7 Basic WDT settings 7 2 7 1 Use case 8 2 7 2 Configuring the Basic WDT 9 2 8 Clearing the basic WDT 11 2 8 1 Use case 12 2 8 2 Example flow to clear the basic WDT 12 2 9 Rese...

Страница 2: ...8 2 Example flow to clear the MCWDT 22 3 8 3 Example program to clear the MCWDT 24 3 9 MCWDT fault handling 24 3 9 1 Use case 24 3 9 2 Example flow of MCWDT fault handler 25 3 10 Reset cause indication for MCWDT 26 3 11 MCWDT registers 27 4 Debug support 28 5 Definitions acronyms and abbreviations 29 6 Related documents 30 7 Other references 31 Revision history 32 ...

Страница 3: ... mode which allows defining an upper and lower time limit within which the watchdog timer must be served The Basic WDT is activated by hardware after reset release Its operation mode is set by the application software during the initial setting It counts in Active Sleep DeepSleep and Hibernate power modes The MCWDT is activated and configured by the application software It counts in Active Sleep a...

Страница 4: ...rmation WDT 32 bit Up Counter WDT_CNT ILO0 INTERRUPT CTL_ENABLE EN SERVICE Write from Firmware Count 0 RESET Count LOWER_LIMIT Count 3 Count UPPER_LIMIT Count WARN_LIMIT Count 32 Debug_active Debug WDT_CONFIG WARN ACTION UPPER ACTION LOWER ACTION Figure 2 Basic WDT block diagram Depending on the configuration in the WDT_CONFIG register an interrupt or a reset event can be generated when the counte...

Страница 5: ...WDT registers are locked 2 4 Warning interrupt The basic WDT supports a WARN limit that can be used to define a dedicated timing to generate an interrupt It can be used for different purposes such as follows Pre warning event The WARN_LIMIT value is defined as lower than the UPPER_LIMIT value It is enabled if the WARN_ACTION 8 bit in the CONFIG register is set to 1 Note that you should use adequat...

Страница 6: ..._LIMIT register for generating a reset if the basic WDT is not serviced in time Set the UPPER_ACTION 4 bit in the CONFIG register to 1 to trigger a reset when the watchdog counter matches with the UPPER_LIMIT value The WARN_LIMIT register can be used as a pre warning event to indicate an incorrect watchdog counter service timing Set the WARN_ACTION 8 bit in the CONFIG register to 1 to enable the w...

Страница 7: ...hdog is not serviced before the upper limit of the basic WDT counter is reached a reset is issued The two limits define the window timing within which the basic watchdog timer must be serviced To enable this function the LOWER_ACTION 0 bit in the CONFIG register must be set to 1 and an adequate lower limit period must be defined in the LOWER_LIMIT register The following example calculates the LOWE...

Страница 8: ...isters Configure Auto Service 1 2 3 4 5 6 7 8 9 11 12 13 Configure Counter Pausein Debug Mode 10 Clear Pending Interrupt End Enable Interrupt System Interrupt Control Enable NVIC Interrupt Controller Setup Interrupt WDT Warn Interrupt Clear NVIC Pending Register 14 15 16 Configure Interrupt Figure 5 Example flow to configure basic WDT 2 7 1 Use case This section explains an example of the basic WD...

Страница 9: ...mit unsigned integer 32 bit 4096ul Cy_WDT_SetUpperLimit Sets the upper limit unsigned integer 32 bit 32768ul Cy_WDT_SetWarnLimit Sets the warn limit unsigned integer 32 bit 28672ul Cy_WDT_SetLowerAction Sets the lower action to no action or reset CY_WDT_LOW_UPP_ACTION_NONE 0ul CY_WDT_LOW_UPP_ACTION_RESET 1ul CY_WDT_LOW_UPP_ACTION_RE SET Cy_WDT_SetUpperAction Sets the upper action to no action or r...

Страница 10: ...reason for device restart if CYHAL_SYSTEM_RESET_WDT cyhal_system_get_reset_reason It s WDT reset event blink LED twice cyhal_gpio_write CYBSP_USER_LED CYBSP_LED_STATE_ON cyhal_system_delay_ms 100 cyhal_gpio_write CYBSP_USER_LED CYBSP_LED_STATE_OFF cyhal_system_delay_ms 200 cyhal_gpio_write CYBSP_USER_LED CYBSP_LED_STATE_ON cyhal_system_delay_ms 100 cyhal_gpio_write CYBSP_USER_LED CYBSP_LED_STATE_O...

Страница 11: ...on time of a low priority main function Figure 6 shows an example of when the watchdog counter can be cleared within a system with different tasks The calculation of each service moment must consider the following conditions 1 In the window mode do not service the watchdog before the counter reaches the LOWER_LIMIT 2 Must service the watchdog counter before reaching the UPPER_LIMIT to avoid a rese...

Страница 12: ... the basic WDT using the use case discussed in 2 7 1 Use case 2 8 2 Example flow to clear the basic WDT Figure 7 shows an example flow to clear the basic WDT Start Clear Basic WDT Counter Clear Basic WDT Interrupt End Set Service bit to clear WDT Counter Unlock Basic WDT Registers Lock Basic WDT Registers 1 2 3 4 5 Figure 7 Example flow to clear the basic WDT 2 9 Reset cause indication for the bas...

Страница 13: ...it Register WDT_UPPER_LIMIT WDT Upper Limit Register WDT_WARN_LIMIT WDT Warn Limit Register WDT_CONFIG WDT Configuration Register WDT_CNT WDT Count Register WDT_LOCK WDT Lock Register WDT_SERVICE WDT Service Register WDT_INTR WDT Interrupt Register WDT_INTR_SET WDT Interrupt Set Register WDT_INTR_MASK WDT Interrupt Mask Register WDT_INTR_MASKED WDT Interrupt Masked Register CLK_ILO0_CONFIG ILO0 co...

Страница 14: ...x_CTR1_UPPER_LIMIT Count MCWDTx_CTR1_WARN_LIMIT 16 MCWDTx_CNT0 16 bit Counter Subcounter 0 Count MCWDTx_CTR0_LOWER_LIMIT Count 3 Count MCWDTx_CTR0_UPPER_LIMIT Count MCWDTx_CTR0_WARN_LIMIT Count 16 INTERRUPT Timeout RESET 32 5 MCWDTx_CTR2_CONFIG BITS MCWDT Mode Configuration MCWDTx_INTR CTR2_INT MCWDTx_CTR2_CONFIG ACT ION MCWDTx_CNT1 16 bit Counter Subcounter 1 Count MCWDTx_CNT2 32 bit Counter Subc...

Страница 15: ...to the related CPU when the WARN_ACTION 8 bit is set to 1 in the CONFIG register The MCWDT can be serviced automatically by the AUTO_SERVICE 12 bit in the CONFIG register This allows the creation of a periodic interrupt if this counter is not needed as a watchdog 3 3 2 MCWDT Subcounter 2 interrupt Subcounter 2 interrupt behaves in a different way A coarse grained timing should be generated when a ...

Страница 16: ...the window mode is shown when FAULT_THEN_RESET is selected as LOWER_ACTION and UPPER_ACTION Four scenarios are possible while LOWER_ACTION WARN_ACTION and UPPER_ACTION are activated accordingly Counter is serviced between LOWER_LIMIT and WARN_LIMIT This is the regular behavior of the MCWDT No WARN interrupt is issued and no RESET is done Counter is serviced between WARN_LIMIT and UPPER_LIMIT The s...

Страница 17: ...low power mode The counter pauses while the respective CPU is in a low power mode if the SLEEPDEEP_PAUSE 30 bit is set to 1 in the CTR2_CONFIG register A single MCWDT is not intended to be used simultaneously by multiple CPUs because of the complexity involved in coordination CPU_SEL 1 0 bits in the CPU_SELECT register are defined in Table 3 Table 3 MCWDT assignment to cores CPU_SEL 1 0 CPU 0 CM0 ...

Страница 18: ...gure NVIC Priority Register 5 6 7 8 9 10 11 12 13 Configure MCWDT Parameters Clear Fault Status 1 2 MCWDT Setting Enable Fault MCWDT Enable Fault Interrupt 3 4 Configure Interrupt Configure Fault Figure 10 Multi counter WDT setting procedure 3 7 1 Use case This section explains an example of the MCWDT using the following use case The MCWDT is cleared in the main task loop The fault interrupt is tr...

Страница 19: ...ounter 1 Same as Subcounter 0 Subcounter 2 Action Interrupt Auto service Enable Deep Sleep Pause Enable Debug mode Enable 3 7 2 Configuring the MCWDT You can configure the parameters in Peripherals tab of the Device Configurator as shown below then ModusToolbox generates the corresponding code automatically Double click design modus to open the Device Configurator ...

Страница 20: ...and initial fault setting procedure see the Interrupt and Fault Report Structure section in AN234226 listed in Related documents Code Listing 2 Example program to configure MCWDT cy_stc_sysint_t mcwdt_irq_cfg intrSrc NvicMux3_IRQn 16 srss_interrupt_mcwdt_0_IRQn intrPriority 2UL int main void cy_rslt_t result cy_en_mcwdt_status_t mcwdt_init_status CY_MCWDT_SUCCESS Initialize the device and board pe...

Страница 21: ...f mcwdt_init_status CY_MCWDT_SUCCESS handle_error Sets up the interrupt handler Cy_SysInt_Init mcwdt_irq_cfg ISR_MCWDT_0 Enable the MCWDT interrupt in NVIC NVIC_EnableIRQ IRQn_Type NvicMux3_IRQn Enable the MCWDT_0 counters Cy_MCWDT_Unlock MCWDT_0_HW Cy_MCWDT_SetInterruptMask MCWDT_0_HW CY_MCWDT_CTR_Msk Cy_MCWDT_Enable MCWDT_0_HW CY_MCWDT_CTR_Msk 0u Cy_MCWDT_Lock MCWDT_0_HW Print a message on UART ...

Страница 22: ...lation of software components is crucial to define the limits of the counter to be cleared The window mode makes it even more complex because a minimum time period needs to be determined before which the software is not expected to service the MCWDT This minimum period can be for example the minimum execution time of a low priority main function and it is relevant to detect the abnormal situation ...

Страница 23: ...2022 05 25 Using the Watchdog Timer in XMC7000 family MCUs Multi counter WDT Start Unlock MCWDT Registers Set Service bit to clear MCWDT Counter Lock Basic MCWDT Registers 1 2 3 Initialization Main Task Figure 11 Example flow to clear the MCWDT ...

Страница 24: ...ct fault cause Different MCWDT instances have independent fault reports so they can be handled by different processors The initialization of fault reporting is shown in Figure 10 and Code Listing 2 As an example Fault structure 1 is used For details of the fault setting procedure see the Fault Report Structure section in AN234226 listed in Related documents The fault is handled within a FAULT repo...

Страница 25: ...ower Limit Fault Subcounter 0 Upper Limit Fault Subcounter 1 Lower Limit Fault Subcounter 1 Upper Limit Fault Subcounter 0 Lower Limit Fault Handling Created by User with User System Requirement Subcounter 0 Upper Limit Fault Handling Created by User with User System Requirement Subcounter 1 Lower Limit Fault Handling Created by User with User System Requirement Subcounter 1 Upper Limit Fault Hand...

Страница 26: ...ndled in time When the device comes out of reset it is useful to know the cause of the reset Reset causes are recorded in the RES_CAUSE register Depending on the MCWDT instance used the reset event is stored in the RESET_MCWDT0 5 RESET_MCWDT1 6 RESET_MCWDT2 7 and RESET_MCWDT3 8 bits in the RES_CAUSE register The bits in the RES_CAUSE register are set on the occurrence of the corresponding reset an...

Страница 27: ...x_CTRy_CONFIG MCWDT Subcounter 0 1 Configuration Register MCWDTx_CTRy_CNTy MCWDT Subcounter 0 1 Count Register MCWDTx_CTR2_CTL MCWDT Subcounter 2 Control Register MCWDTx_CTR2_CONFIG MCWDT Subcounter 2 Configuration Register MCWDTx_CTR2_CNT MCWDT Subcounter 2 Count Register MCWDTx_LOCK MCWDT Lock Register MCWDTx_SERVICE MCWDT Service Register MCWDTx_INTR MCWDT Interrupt Register MCWDTx_INTR_SET MCW...

Страница 28: ...ssued when the debugger is connected to the target system To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for the related WDT It takes up to two LFCLK cycles for the trigger signal to be processed Triggers that are less than two LFCLK cycles may be missed Synchronization errors can accumulate each time it is halted...

Страница 29: ...us CPU Central Processing Unit CPUSS CPU subsystem ECO High frequency crystal oscillator ILO0 32 kHz internal low speed oscillator IRQ Interrupt request ISR Interrupt Service Routine kHz kilohertz LFCLK Low frequency clock MCWDT Multi Counter Watchdog Timer ms msec milliseconds POR Power on reset PPU Peripheral Protection Unit sec second SW Software VDDD External high voltage supply WCO Low freque...

Страница 30: ...upport to obtain these documents Device datasheet Datasheet 32 Bit Arm Cortex M7 Microcontroller XMC7100 Family Doc No 002 33896 Datasheet 32 Bit Arm Cortex M7 Microcontroller XMC7200 Family Doc No 002 33522 Technical Reference Manual TRM XMC7000 Family Architecture Technical Reference Manual TRM Doc No 002 33816 XMC7100 registers technical reference manual TRM Doc No 002 33817 XMC7200 registers t...

Страница 31: ...ces Infineon provides the ModusToolbox CAT1 Peripheral Driver Library including the initialization code as sample software to access various peripherals Code snippets in this application note are part of the ModusToolbox CAT1 Peripheral Driver Library Contact Technical support to obtain the ModusToolbox CAT1 Peripheral Driver Library ...

Страница 32: ...02 33887 Rev A 2022 05 25 Using the Watchdog Timer in XMC7000 family MCUs Revision history Revision history Document version Date of release Description of changes 2021 12 08 Initial release A 2022 05 25 Updated the code listing ...

Страница 33: ...intellectual property rights of any third party with respect to any and all information given in this application note The data contained in this document is exclusively intended for technically trained staff It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in t...

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