Application Note
12 of 33
002-33887 Rev. *A
2022-05-25
Using the Watchdog Timer in XMC7000 family MCUs
Basic WDT
Sequence 2:
250ms
...
125ms
Time
LOWER_LIMIT = 0x1000
Counts value
0xFFFFFFFF
UPPER_LIMIT = 0x8000
Sequence 1:
750ms
Ta
sk
1
Ta
sk
2
Ta
sk
3
Ta
sk
4
Ta
sk
1
Ta
sk
4
Ta
sk
1
Ta
sk
4
Ta
sk
5
Ta
sk
1
Ta
sk
2
100ms 300ms 200ms 150ms 100ms 150ms 100ms 150ms 200ms 100ms 300ms
SERVICE
SERVICE
SERVICE
Sequence 3:
450ms
Figure 6
Example of servicing the basic WDT in window mode
2.8.1
Use case
This section describes an example of clearing the basic WDT using the use case discussed in
2.8.2
Example flow to clear the basic WDT
shows an example flow to clear the basic WDT.
Start
Clear Basic WDT Counter
Clear Basic WDT Interrupt
End
Set Service bit to clear WDT Counter
Unlock Basic WDT Registers
Lock Basic WDT Registers
(1)
(2)
(3)
(4)
(5)
Figure 7
Example flow to clear the basic WDT
2.9
Reset cause indication for the basic WDT
If the basic WDT is not serviced or serviced too early, a system-wide reset is issued. The reset event is stored in
the RESET_WDT[0] bit in the RES_CAUSE register.
Note:
The hardware clears this bit during power-on reset (POR). It cannot be distinguished whether a
reset was caused by a LOWER_LIMIT or UPPER_LIMIT violation.
