Infineon XENSIV BGT60LTR11AIP, Руководство пользователя

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Application Note page 19 of 33 V1.7
2022-08-01
XENSIV™ BGT60LTR11AIP shield
60 GHz radar system platform
Radar MMIC settings configuration
4.3 Detector hold time
The internal detector hold time, is the time for which the internal detector outputs remain active after target
detection.
Autonomous mode
QS3 is used to select the detector hold time value for the autonomous mode. In order to have up to 16 hold
time values, the PLL_TRIG should be conn
ected to VDD by removing R6 and placing R18 = 0 Ω. This will put the
MMIC into “Advance mode” . The default QS3 setting on the shield for the hold time is 1s. Recommended
resistor values for changing the QS3 on the autonomous shield are detailed in Table 6.
Table 6 QS3 settings
Resistors setting
Detector Hold time
R19 R20
10 kΩ 330 Ω Minimum (16 ms, 32 ms, 64 ms or 128 ms) dep. on PRT
10 kΩ 1 kΩ 500 ms
10 kΩ 1.8 kΩ 1 s
10 kΩ 2.7 kΩ 2 s
10 kΩ 3.9 kΩ 3 s
10 kΩ 5.6 kΩ 5 s
10 kΩ 6.8 kΩ 10 s
10 kΩ 8.2 kΩ 30 s
10 kΩ 12 kΩ 45 s
10 kΩ 15 kΩ 1 min
10 kΩ 18 kΩ 90 s
10 kΩ 27 kΩ 2 min
10 kΩ 39 kΩ 5 min
10 kΩ 56 kΩ 10 min
10 kΩ 100 kΩ 15 min
10 kΩ 22 0 kΩ 30 min
SPI mode
In SPI operation mode, the user can set the internal detector hold time by writing to hold (Reg10[15:0]) bit fields
of the MMIC SPI registers.