Data Sheet
58
Rev. 1.00
2017-07-31
TLE9262-3BQX
5.4.8.2
Setup of Clock and Data Recovery
It is strongly recommended to enable the clock and data recovery feature only when the setup of the clock and
data recovery is finished.
The following sequence should be followed for enabling the clock and data recovery feature:
• Step 1: Switch CAN to OFF and
CDR_EN
to OFF
Write SPI Register
BUS_CTRL_1
(CAN[2:0] = 000).
• Step 2: Configure CDR Input clock frequency
Write SPI Register
SWK_CDR_CTRL2
(SEL_OSC_CLK[1:0]).
• Step 3: Configure Bit timing Logic
Write SPI Register
SWK_BTL1_CTRL
and adjust
SWK_CDR_LIMIT_HIGH_CTRL
and
SWK_CDR_LIMIT_LOW_CTRL
according to
Table 38
.
• Step 4: Enable Clock and Data Recovery
Choose filter settings for Clock and Data recovery. Write SPI Register
SWK_CDR_CTRL1
with
CDR_EN
= 1
Additional hints for the CDR configuration and operation:
• Even if the CDR is disabled, when the baud rate is changed, the settings of
SEL_OSC_CLK
in the register
SWK_CDR_CTRL1
and
SWK_BTL1_CTRL
have to be updated accordingly,
• The
SWK_CDR_LIMIT_HIGH_CTRL
and
SWK_CDR_LIMIT_LOW_CTRL
registers have to be also updated
when the baud rate or clock frequency is changed (the CDR is discarding all the acquisitions and looses all
acquired information, if the limits are reached - the
SWK_BTL1_CTRL
value is reloaded as starting point
for the next acquisitions)
• When updating the CDR registers, it is recommended to disable the CDR and to enable it again only after
the new settings are updated,
• The
SWK_BTL2_CTRL
register represents the sampling point position. It is recommended to be used at
default value: 11 0011 (~80%)
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