Application Note
16
2011-07-06
In addition to the latch-off enable function, this pin is also built for the selection of burst mode enable or
not during
configuration before softstart. If the burst mode is enabled, the gate drives will be disabled if
LOAD pin voltage falls below 0.12V. However, if burst mode is not selected, the gate drives will not be
stopped by LOAD pin voltage.
The selection block works only after the first time IC VCC increases above UVLO. After CVCC is higher
than turn on threshod, a current source
sele
I
, in addition to the
EnA
I
, is turned on to charge the capacitor
EnA
C
. After 26
μ
s, IC will compare the voltage on EnA pin and 1.0V, if voltage on EnA pin is higher than
1.0V, the burst mode function will be enabled. As the voltage on EnA pin depends on
EnA
R
and
EnA
C
, by
selecting different capacitance value, whether this IC works with burst mode can be decided.
With
Ω
=
M
R
EnA
1
and
nF
C
EnA
1
=
, the voltage at EnA pin at the time of 26us can be calculated as:
Therefire burst mode will be enabled. If
EnA
C
is set to be 10n F, thus burst
mode will be disabled.
After the selection is done, the current source
sele
I
is turned off. A blanking time of 320
μ
s is given before
IC starts to sense the EnA pin voltage latch off enable purpose. This blanking time is used to let the EnA
pin votlage be stablized to avoid mistriggering of Latch-off Enable function.
2.4
Design of Synchronous Rectification (SR) control
Synchronous Rectification (SR) in a half-bridge LLC resonant converter is one of the key factor to achieve
high efficiency. SR control is a major benefit we offer with our new LLC controller IC ICE2HS01G.
Before going into details of SR control of the IC, it’s necessary to understand the ideal SR switching
mechanism for two typical working conditions, i.e. when operation frequency(
sw
f
) is below (
sw
f
<
r
f
)
and above the resonant frequency (
sw
f
>
r
f
).Figure 7 illustrates the waveforms of
HG
V
(primary high side
gate),
LG
V
(primary low side gate),
SHG
V
( secondary high side gate),
SLG
V
(secondary low side gate),
SH
I
(current flowing through secondary high side MOSFET),
SL
I
( current flowing through secondary low
side MOSFET) and
PRI
I
(current flowing through primary resonant tank).
V
V
e
e
R
I
V
RC
EnA
sele
EnA
0
.
1
56
.
2
)
1
(
*
10
*
10
*
100
)
1
(
*
9
6
6
6
10
*
10
10
*
26
6
6
10
*
26
>
=
−
=
−
=
−
−
−
−
−
−
us
V
V
V
EnA
26
@
0
.
1
26
.
0
<
=