Infineon Cypress S29GL01GS, Руководство пользователя

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Document Number: 001-98285 Rev. *R Page 79 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Note:
1. Not 100% tested.
Note:
1. Not 100% tested.
t
OEH
Output Enable Hold Time
(Note 1)
Read Min 0 ns
Toggle and
Data# Polling
Min 10 ns
t
ASSB
Automatic Sleep to Standby time (Note 1)
CE# = V
IL
,
Address stable
Typ 5 µs
Max 8 µs
Table 11.5 Read Operation V
IO
= V
CC
= 2.7 V to 3.6 V (–40 °C to +105 °C)
Parameter
Description Test Setup
Speed Option
Unit
JEDEC Std 100 110 120
t
AVAV
t
RC
Read Cycle Time (Note 1)
128 Mb, 256 Mb
Min
100 110 –
ns
512 Mb, 1 Gb – 110 120
t
AVQV
t
ACC
Address to Output Delay
CE# = V
IL
OE# = V
IL
128 Mb, 256 Mb
Max
100 110 –
ns
512 Mb, 1 Gb – 110 120
t
ELQV
t
CE
Chip Enable to Output
Delay
OE# = V
IL
128 Mb, 256 Mb
Max
100 110 –
ns
512 Mb, 1 Gb – 110 120
t
PACC
Page Access Time
128 Mb, 256 Mb
Max
15 20 –
ns
512 Mb, 1 Gb – 15 20
t
GLQV
t
OE
Output Enable to Output Delay Max 25 ns
t
AXQX
t
OH
Output Hold time from addresses, CE# or
OE#, Whichever Occurs First
Min 0 ns
t
EHQZ
t
DF
Chip Enable or Output Enable to Output
High-Z (Note 1)
Max 15 ns
t
OEH
Output Enable Hold Time
(Note 1)
Read Min 0 ns
Toggle and
Data# Polling
Min 10 ns
t
ASSB
Automatic Sleep to Standby time (Note 1)
CE# = V
IL
, Address
stable
Typ 5 µs
Max 8 µs
Table 11.6 Read Operation V
IO
= 1.65 V to V
CC
, V
CC
= 2.7 V to 3.6 V (–40 °C to +105 °C)
Parameter
Description Test Setup
Speed Option
Unit
JEDEC Std 110 120 130
t
AVAV
t
RC
Read Cycle Time (Note 1)
128 Mb, 256 Mb
Min
110 120 –
ns
512 Mb, 1 Gb – 120 130
t
AVQV
t
ACC
Address to Output Delay
CE# = V
IL
OE# = V
IL
128 Mb, 256 Mb
Max
110 120 –
ns
512 Mb, 1 Gb – 120 130
t
ELQV
t
CE
Chip Enable to Output
Delay
OE# = V
IL
128 Mb, 256 Mb
Max
110 120 –
ns
512 Mb, 1 Gb – 120 130
Table 11.4 Read Operation V
IO
= 1.65 V to V
CC
, V
CC
= 2.7 V to 3.6 V (–40 °C to +85 °C) (Continued)
Parameter
Description Test Setup
Speed Options
Unit
JEDEC Std 100 110 120