Document Number: 001-98285 Rev. *R
Page 88 of 108
S29GL01GS/S29GL512S
S29GL256S/S29GL128S
Figure 11.18
Toggle Bit Timing Diagram (During Embedded Algorithms)
Note:
1. DQ6 will toggle at any read address while the device is busy. DQ2 will toggle if the address is within the actively erasing sector.
Figure 11.19
DQ2 vs. DQ6 Relationship Diagram
Note:
1. The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-suspended sector.
11.4.3
Alternate CE# Controlled Write Operations
Table 11.10
Alternate CE# Controlled Write Operations
Parameter
Description
V
IO
= 2.7 V
to V
CC
V
IO
= 1.65 V
to V
CC
Unit
JEDEC
Std
t
AVAV
t
WC
Write Cycle Time
Min
60
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# Low during toggle bit
polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold Time From CE# or OE# High during
toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
30
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
CEPH
CE# High during toggle bit polling
Min
20
ns
t
0EPH
OE# High during toggle bit polling
Min
20
ns
OE#
CE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read)
(second read)
(stops toggling)
t
CEPH
t
AHT
t
AS
DQ2 and DQ6
Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing