CPU_
4
2
A
-V1
CPU Boar
d X
M
C42
0
0
A
c
tu
a
to
r
P
ro
d
u
ctio
n
D
ata
B
oa
rd
Us
er'
s
Ma
n
ua
l
24
Rev
is
io
n 1
.0
,
2
01
3
-02
-19
2
.1
2
.1
A
C
T
S
a
tell
ite
Con
nec
to
r
T
he
A
CT
s
ate
llite
c
o
nn
ec
to
r on
th
e
C
P
U_4
2A
-V1
bo
ar
d
al
lo
w
s
int
erf
ac
e e
x
pa
ns
io
n t
hrou
gh
A
CT
s
ate
llit
e c
ar
ds
.
XMC
Pin
VSS
P1.3
P1.2
P1.1
nc
nc
nc
nc
nc
P1.0
nc
nc
P0.6
P2.0
nc
nc
nc
nc
P2.4
nc
PORST
VAREF
P14.8
P14.6
nc
nc
P14.5
nc
nc
P0.5
P0.2
P0.4
P0.1
P0.3
P0.0
P2.3
P2.2
VSS
XMC Function
GND
POSIF0.IN0A/HRPWM0.C0INB
POSIF0.IN1A/HRPWM0.C2INA
POSIF0.IN2A/HWPWM0.C1INA
nc
nc
nc
nc
nc
CCU40.IN3A/HRPWM0.C0INA
nc
nc
P0.6
P2.0/CCU40.IN1C
2-pin Jumper
nc
nc
nc
U0C1.SCLKOUT
nc
RESET#
VAREF
VADC_G1CH0
VADC_G0CH6
nc
nc
VADC_G0CH5
nc
nc
CCU80.OUT00/HROUT00
CCU80.OUT01/HROUT01
CCU80.OUT10/HROUT21
CCU80.OUT11
CCU80.OUT20/HROUT20
CCU80_OUT21
CCU41_OUT2
CCU41_OUT3
GND
Function
GND
PIF0IN1
PIF0IN2
PIF0IN3
DSDIN0
DSDIN1
DSDIN2
DSDIN3
RSVD
CC_IN0
CC_IN1
CC_IN2
ENA_A
ENA_B
ENA_X
SPI_MTSR
SPI_MRST
SPI_SCLK
I2C_SCL
GPIO
RESET
VDD5
VDD5
AREF
DAC1/ADC0
ADC2/DACREF
ADC4/ORC1
ADC6/ORC3
ADC8
ADC10
ADC12
PWMA0_H
PWMA0_L
PWMA1_H
PWMA1_L
PWMA2_H
PWMA2_L
PWMX0
PWMX1
GND
Sate
ll
it
e
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
Conn
ect
or
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
Function
GND
PIF1IN0
PIF1IN1
PIF1IN2
PWMN
PWMP
DSDCLK0
DSDCLK1
RSVD
CC_IN3
CC_IN4
CC_IN5
TRAP_A
TRAP_B
TRAP_X
SPI_CSA0
SPI_CSA1
SPI_CSA2
I2C_SDA
ACT_GPIO1
ACT_GPIO0
VDD5
VDD5
AGND
DAC0/ADC1
ADC3/ORC0
ADC5/ORC2
ADC7
ADC9
ADC11
ADC13
PWMB0_H
PWMB0_L
PWMB1_H
PWMB1_L
PWMB2_H
PWMB2_L
PWMX2
PWMX3
GND
XMC Function
GND
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
CCU80.IN0A
nc
nc
nc
nc
nc
U0C1.DX0B/DOUT0
nc
nc
AGND
VADC_G1CH1
nc
VADC_G0CH0 (4)
nc
nc
VADC_G1CH3
nc
nc
nc
nc
nc
nc
nc
HRPWM0.HROUT10
HRPWM0.HROUT11
GND
XMC Pin
VSS
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
P0.7 (1,6)
nc
nc
nc
nc
nc
P2.5
nc
nc
VAGND
P14.9
nc
P14.0
nc
nc
P14.3
nc
nc
nc
nc
nc
nc
nc
P0.7 (1)
P0.8 (2)
VSS
Pin
ACT
ACT
ACT
CPU
_4
2A-V1
CPU
_4
2A-V1
F
igu
re 2
2
S
atell
it
e Con
n
ec
to
r T
y
p
e
A
CT
(1)
P
0
.7
c
a
n
a
ls
o
b
e
u
s
e
d
fo
r J
T
A
G
D
e
b
u
g
g
ing
(TD
I)
(2)
P
0
.8
is
u
s
e
d
a
s
TR
S
T
in
o
rd
e
r t
o
e
n
a
b
le
J
T
A
G
D
e
b
u
g
(3)
This
p
in
is
c
o
n
n
e
c
te
d
w
it
h
th
e
s
a
te
llit
e
c
o
n
n
e
c
to
r v
ia
an
a
n
a
log
s
w
it
c
h
(4)
This
A
D
C
inp
ut
do
es
n
ot
su
pp
ort
“Ou
t o
f R
an
ge
D
ete
ction
”
(5)
This
p
in
m
us
t b
e “
en
ab
led
” b
y a
so
lde
r ju
m
p
.
(6)
S
u
p
p
o
rt
H
igh
R
e
s
o
lut
ion
P
W
M
3
Pr
o
d
u
cti
o
n
D
ata
3
.1
S
c
hem
a
ti
c
s
T
hi
s
c
ha
pte
r c
on
tai
ns
t
he
s
c
he
m
ati
c
s
for the
CP
U b
oa
rd:
S
ate
llite
Co
nn
ec
tor
,
US
B
,
CA
N
X
MC42
00
P
o
w
er
an
d
Deb
ug
On
-bo
ard D
eb
u
gg
er
T
he
bo
ard h
as
be
en
d
es
ig
n
ed
wi
th
E
ag
le
.
T
he
f
ul
l P
CB
de
s
ig
n d
ata
of
th
is
bo
ard
c
an
a
ls
o b
e d
o
wnl
oa
de
d f
ro
m
www.i
