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BGT24MTR11 

 

User's Guide 

 

 

  

VCO Section 

Application Note AN305, Rev. 1.0 

2012-11-15 

8 / 15 

3.2 

Prescalers 

 

BGT24MTR11 has two cascaded built-in prescalers. 

The first prescaler divides the oscillator’s frequency by 16, 

the  second  reduces  the  output  of  the  first  one  by  the  factor  of  65536 

–  resulting  in  a  total  division  factor  of 

1,048,576. 

3.2.1 

Divide-by-16 Prescaler 

This first prescaler divides the VCO’s frequency of oscillation by the factor of 16. So at a given  VCO frequency 
of 24 

GHz the prescaler’s output frequency is 1.5 GHz. This is a convenient frequency to feed into RF-PLLs. 

The output frequency is fed differentially to pins 31 and 1 (Q1, Q1N). The differential port impedance is 100 

 

Note: For  proper  operation  of  the  prescaler  both  output  pins  need  to  be  terminated  by  50 

.  As  there  is  DC 

present  at  the  two  output  pins  a  coupling  capacitor  will  be  necessary  if  the  termination  does  not  have  a 
DC-blocking circuit already implemented, (e.g. 

a blocking capacitor at a PLL’s input). 

In case a PLL does not support differential inputs it is possible to use any of the two outputs and terminate the 
unused one. 

 

 

Figure 5 

Termination of Div16 outputs 

This prescaler may be disabled by setting SPI data bit 5 (DIS_DIV16) to HIGH. 

3.2.2 

Divide-by-65536 Prescaler 

This  prescaler  is  fed  by  the  divide-by-16  prescal

er’s  output frequency  and reduces it furtherly by  the factor of 

65536 resulting in a total reduction factor of 1,048,576. This means a 24 GHz VCO signal will result in an output 
square wave signal of approximately 23 kHz at pin 2 (Q2). 

This 23 kHz output signal  c

an be monitored via a microcontroller’s timer input, for example, and then be used 

together  with  the  microcontrollers  DAC  or  PWM  output  to  create  a 

software  loop  to  control  the  VCO’s  output 

frequency. 

 

Note: For proper operation of this prescaler it is mandatory that the divide-by-16 prescaler is enabled. Otherwise 

the divide-by-65536 will not get an input signal and will produce false output. 

This prescaler may be disabled by setting SPI data bit 6 (DIS_DIV64k) to HIGH. 

BGT24MTR11_Q1_connect.vsd

TEMP

Q1

VEE

Q

1

N

Q

2

V

E

E

1

2

3

30

31

32

50

Ω

50

Ω

Содержание BGT24MTR11

Страница 1: ...RF and Protection Devices BGT24MTR11 Application Note AN305 Revision Rev 1 0 2012 11 15 User s Guide to BGT24MTR11 24 GHz Radar...

Страница 2: ...ry terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For infor...

Страница 3: ...hip Bluetooth of Bluetooth SIG Inc CAT iq of DECT Forum COLOSSUS FirstGPS of Trimble Navigation Ltd EMV of EMVCo LLC Visa Holdings Inc EPCOS of Epcos AG FLEXGO of Microsoft Corporation FlexRay is lice...

Страница 4: ...5 Receiver Section 11 5 1 Low Noise Amplifier 11 5 2 Mixer 11 6 Sensors 12 6 1 Power Sensors 12 6 2 Temperature Sensor 13 Authors 14 List of Figures Figure 1 BGT24MTR11 block diagram 5 Figure 2 VCO fr...

Страница 5: ...nd BGT24MR2 as well The additional information in this application note is valid for these products as well 2 Overview The picture below shows the internal block diagram of BGT24MTR11 Figure 1 BGT24MT...

Страница 6: ...resistor to Vcc This means that when a pin is left open it will be internally at Vcc So if both pins are left open the oscillator will be around 26 GHz at room temperature Note It is mandatory for eac...

Страница 7: ...s VCOARSE and VFINE Figure 4 2D plot Output voltage vs VCOARSE and VFINE 0 0 25 0 5 0 75 1 1 25 1 5 1 75 2 2 25 2 5 2 75 3 3 25 0 0 25 0 5 0 75 1 1 25 1 5 1 75 2 2 25 2 5 2 75 3 3 25 25 C Vfine V V co...

Страница 8: ...capacitor at a PLL s input In case a PLL does not support differential inputs it is possible to use any of the two outputs and terminate the unused one Figure 5 Termination of Div16 outputs This pres...

Страница 9: ...rminate one of the TX outputs with 50 and use the other one directly as a 50 output port However this will reduce the available output power by 3 dB Note It is not recommended to create a 100 single e...

Страница 10: ...l loop can re lock the frequency again There are two possibilities to turn on and off the TX ouput power The first is via the SPI bus and the second is using the TXOFF pin 4 1 1 1 Enabling disabling v...

Страница 11: ...4 PC2_BUF of the SPI register to HIGH In low output power mode the output power is reduced by 3 5 dB In case the LO output is not required this pin can be left open 5 Receiver Section BGT24MTR11 s rec...

Страница 12: ...ak voltage detectors are connected to the output of the TX power amplifier and to the LO medium power amplifier To eliminate temperature and supply voltage variations a reference output voltage VREF i...

Страница 13: ...age can be read out via the analog multiplexer output ANA pin 25 The temperature sensor can be independently biased through VCCTEMP pin 29 This makes it possible to measure the chip temperature while...

Страница 14: ...BGT24MTR11 User s Guide Authors Application Note AN305 Rev 1 0 2012 11 15 14 15 Authors Dietmar Stolz Staff Engineer of Business Unit RF and Protection Devices...

Страница 15: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG AN305...

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