Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-240 V1.1, 2011-05
GPTA
®
v5, V1.14
Two LTC Input Multiplexer Control Registers, LIMCRL (see also Page 21-266 and
Page 21-267 ), are assigned to each of the LTC groups. Therefore, in total eight registers
control the connections within the LTC input multiplexer of the LTCA unit.
The LIMCRL registers control the LIMG output lines 0 to 3 and the LIMCRH registers
control the LIMG output lines 4 to 7.
Table 21-22 lists all LTC Input Multiplexer Control
Registers with its control functions. Please note that all LTC Input Multiplexer Control
Registers are not directly accessible but must be written or read using a FIFO array
structure as described on
Page 21-121 .
21.5.2.3 Multiplexer Register Array Programming
A total of 24 control registers are required to program the configuration of the output
multiplexer and the LTC input multiplexer of the Input/Output Line Sharing Block. These
IOLS control registers are combined into a Multiplexer Register Array FIFO that can only
be read or written sequentially. Therefore, the control registers values cannot be
accessed directly but must be accessed in a specific sequential order.
Three registers are available for controlling the Multiplexer Register Array:
•
Multiplexer Register Array Control Register MRACTL
• Multiplexer Register Array Data Out Register MRADOUT
• Multiplexer Register Array Data In Register MRADIN
Figure 21-90 shows the structure of the multiplexer array FIFO with the arrangement of
the multiplexer control registers.
For programming of the multiplexer array FIFO, the following steps must be executed:
1. Disable interconnections of the multiplexer array by writing MRACTL.MAEN = 0
(default after reset). The multiplexer array is disabled, all cell input lines are driven
with 0, and device pins assigned to LTCA I/O lines or output lines are disconnected.
2. Reset the write cycle counter to 0 by writing MRACTL.WCRES = 1.
Table 21-22 LTC Input Multiplexer Control Register Assignments
LTC Group and LTCs Controlled by Register Selectable Groups via LIMGng
LTCG0 LTC[03:00] LIMCRL0 IOG0, CLOCK, PDL/INT
LTC[07:04] LIMCRH0
LTCG1 LTC[11:08] LIMCRL1 IOG1, CLOCK, PDL/INT
LTC[15:12] LIMCRH1
LTCG2 LTC[19:16] LIMCRL2 IOG2, CLOCK, PDL/INT
LTC[23:20] LIMCRH2
LTCG3 LTC[27:24] LIMCRL3 IOG3, CLOCK, PDL/INT
LTC[31:28] LIMCRH3