Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-121 V1.1, 2011-05
GPTA
®
v5, V1.14
21.3.4.6 Multiplexer Register Array Programming
A total of 54 control registers are required to program the configuration of the output
multiplexer, the On-chip trigger and gating multiplexer, and the two input multiplexers of
the Input/Output Line Sharing Block. These IOLS control registers are combined into a
Multiplexer Register Array FIFO that can only be read or written sequentially. Therefore,
the control registers values cannot be accessed directly but must be accessed in a
specific sequential order.
Three registers are available for controlling the Multiplexer Register Array:
•
Multiplexer Register Array Control Register MRACTL
• Multiplexer Register Array Data In Register MRADIN
• Multiplexer Register Array Data Out Register MRADOUT
Figure 21-78 shows the structure of the multiplexer array FIFO with the arrangement of
the multiplexer control registers.
For programming of the multiplexer array FIFO, the following steps must be executed:
1. Disable interconnections of the multiplexer array by writing MRACTL.MAEN = 0
(default after reset). The multiplexer array is disabled, all cell input lines are driven
with 0, and device pins assigned to GPTA
®
v5 I/O lines or output lines are
disconnected.
2. Reset the write cycle counter to 0 by writing MRACTL.WCRES = 1.
3. Write sequentially the multiplexer control register contents one after the other
(54 values) into MRADIN, starting with the register values for OTMCR1, OTMCR0,
… up to GIMCRH0, GIMCRL0 (see
Figure 21-78 ). After the first MRADIN write
operation, the contents for OTMCR1 is at FIFO position 1. With each following
MRADIN write operation, it becomes shifted one FIFO position upwards. After the 54.
MRADIN write operation, the OTMCR1 value is at its final position. The contents of
FIFO position 54 can be read via register MRADOUT. With each MRADIN write
operation the write cycle counter MRACTL.FIFOFILLCNT is incremented by 1. After
all FIFO entries have been written, the FIFO is locked, bit MRACTL.FIFOFULL is set,
and further MRADIN write operations are discarded until bit MRACTL.WCRES is
written again with a 0.
4. Enable the multiplexer array by writing MRACTL.MAEN = 1. This establishes and
enables all programmed interconnections.
To check the FIFO contents, the FIFO can be written a second time. At this check
MRADIN is written before MRADOUT is read. This will return the FIFO contents of the
first write sequence in the order of OTMCR1, OTMCR0, …, GIMCRH0, GIMCRL0.
Before disabling the multiplexer array FIFO, GPTA
®
v5 output pins that are already
enabled as GPTA
®
v5 output should be switched to GPIO function to avoid output spikes.
After enabling the multiplexer array FIFO again, the GPTA
®
v5 output can be switched
again back to GPTA
®
v5 output function.