MB39C503-EVBSK-01 Evaluation Board Operation Manual, Doc. No. 002-08718 Rev. *B
12
7. Circuit Diagram
Figure 7-1 Circuit Diagram
VCC
FB
PWRGD
ALERT_N
VIN
VDD
BST
DRVH
CSP
CSN
SLP_N
EN
AGND
ILIM
PGND
DRVL
LX
11
8
9
3
7
2
15
13
16
6
4
5
1
17
10
14
12
M1
G
D
S1
S2
S3
Q1
4
3
2
9
1
G
D
S1
S2
S3
Q1
7
6
5
10
8
1
L1
2
1
NMT
D3
C
1
-1
C
1
-2
C
1
-3
VOUT
C
2
-2
2
1
R2
8
N
M
T
.
.
C
2
-1
1
C8
C7
2
1
C5
2
1
C6
2
1
R4
2
1
LDO5
.
.
PatternShort
R18
EN
1
SLP_N
1
PWRGD
ALERT_N_VOUT
VIN
VIN
VDD
1
R2
2
R
1
-2
2
1
R21
2
1
R
1
5
R1
4
VCC
VCC
R
2
7
2
1
VINs
1
VOUTs
1
VIN
C
2
-1
2
1
PatternShort
VOUT1
PGND1
1
PGNDs
VOUT2
VOUT3
PGND2
PGND3
VIN1
VIN2
VIN3
.
.
R
3
0
VCC
LX
C
2
-3
C
2
-4
C
2
-5
C2
-6
C2
-7
C
2
-8
C
2
-9
C
2
-1
0
VOUT4
PGND4
VIN4
VOUT5
PGND5
R2
9
VCC
1
2
R
1
-1