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©Copyright 2000-2007 SD Card Association
SDIO Simplified Specification Version 2.00
41
8.1.7
Terminated Data Transfer Interrupt Cycle
This section is not included in the Simplified Specification.
8.1.8
Interrupt Clear Timing
Since the SDIO card uses level sensitive interrupts, the host shall clear pending interrupts with an I/O read or
write to some function unique area. In some host implementations, the sending of a CMD52 to the card is
handled by host adapter hardware while the host CPU can execute other operations. This condition may allow
an interrupt that has already been handled to re-interrupt the host if the timing of the interrupt clear is not
controlled. To prevent this condition, Any SDIO card that implements interrupts shall follow some required timing
with respect to removing the interrupt from the DAT[1] line after the write to the function unique area that clears
the interrupt. The clearing of the interrupt can be caused by an I/O write in a function unique method, or by a
function unique I/O read. An example of clearing an interrupt using an I/O read would be a function where the
reading of a data register may automatically clear the data ready interrupt.
The rest of this section is not included in the Simplified Specification.