©Copyright 2000-2007 SD Card Association
SDIO Simplified Specification Version 2.00
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6.
SDIO Card Internal Operation
I/O access differs from memory in that the registers can be written and read individually and directly without a
FAT file structure or the concept of blocks (although block access is supported). These registers allow access to
the I/O data, control of the I/O function and report on status or transfer I/O data to/from the host. The SD memory
relies on the concept of a fixed block length with commands reading/writing multiples of these fixed size blocks.
I/O may or may not have fixed block lengths and the read size may be different from the write size. Because of
this, I/O operations may be based on either a length (byte count) or a block size.
6.1 Overview
Each SDIO card may have from 1 to 7 functions plus one memory function built into it. A function is a self
contained I/O device. I/O functions may be identical or completely different from each other. All I/O functions are
organized as a collection of registers. There is a maximum of 131,072 (2
17
) registers possible for each I/O
function. These registers and their individual bits may be read Only (RO), Write Only (WO) or Read/Write (R/W).
These registers can be 8, 16 or 32 bits wide within the card. All addressing is based on byte access. These
registers can be written and/or read one at a time, multiply to the same address or multiply to an incrementing
address. The single R/W access is often used to initialize the I/O function or to read a single status or data value.
The multiple reads to a fixed address are used to read or write data from a data FIFO register in the card. The
read to incrementing addresses is used to read or write a collection of data to/from a RAM area inside of the
card. Figure 6-1 shows the mapping of the CIA and optional CSA space for an SDIO card.
6.2 Register
Access
Time
All registers in SDIO only cards and the SDIO portion of Combo cards shall complete read and write data
transfer in less than 1 second. This timeout value relates to the time for the requested data to be transferred
to/from the host on the DAT[x] lines and not the timing between the command and the response. This wait time
is signaled to the host by the card using busy for a write or delaying the start bit for a read operation. The host
can use 1 second as the timeout value for a non-responding location. If a functions needs to support an access
time greater than 1 second, the card maker may use some function specific method that is not defined in this
specification.
6.3 Interrupts
All SDIO hosts should support hardware interrupts. If a host does not support interrupts, it may have difficulties
working with SDIO cards that expect fast response to interrupt conditions. Each function within an SDIO or
Combo card may implement interrupts as needed. The interrupt used on SDIO functions is a type commonly
called “level sensitive”. Level sensitive means that any function may signal for an interrupt at any time, but once
the function has signaled an interrupt, it shall not release (stop signaling) the interrupt until the cause of the
interrupt is removed or commanded to do so by the host. Since there is only 1 interrupt line, it may be shared by
multiple interrupt sources. The function shall continue to signal the interrupt until the host responds and clears
the interrupt. Since multiple interrupts may be active at once, it is the responsibility of the host to determine the
interrupt source(s) and deal with it as needed. This is done on the SDIO function by the use of two bits, the
interrupt enable and interrupt pending. Each function that may generate an interrupt has an interrupt enable bit.
In addition, the SDIO card has a master interrupt enable that controls all functions. An interrupt shall only be
signaled to the SD bus if both the function’s enable and the card’s master enable are set. The second interrupt
bit is called interrupt pending. This read-only bit tells the host which function(s) may be signaling for an interrupt.
There is an interrupt pending bit for each function that can generate interrupts. These bits are located in the
CCCR area. For more details, see Table 6-1 and Table 6-2. Interrupt operation is described more fully in section
8.